Architectures for Digital Signal Processing

Digital signal processing (DSP) covers a wide range of applications such as signal acquisition, analysis, transmission, storage, and synthesis. Special attention is needed for the VLSI (very large scale integration) implementation of high performance DSP systems with examples from video and radar applications. This book provides basic architectures for VLSI implementations of DSP tasks covering architectures for application specific circuits and programmable DSP circuits. It fills an important gap in the literature by focusing on the transition from algorithms specification to architectures for VLSI implementations. Areas covered include: architectures for basic operations and elementary functions parallel processing and pipelining application specific array processors programmable digital signal processors With the fusion of signal processing algorithms and VLSI circuit design it will assist digital signal processing architecture developers. This book is of particular interest to electronic engineering and computer science students and will benefit practitioners of digital signal processor circuit design.

Peter Pirsch is the author of Architectures for Digital Signal Processing, published by Wiley.

Preface

ix

1 Introduction

1

(12)

1.1 Signal Processing Algorithms

1

(4)

1.2 Implementation Aspects

5

(4)

1.3 Overview

9

(4)

2 Basic CMOS Circuits

13

(42)

2.1 Transistor Modelling

13

(9)

2.2 Basic Logic Circuits

22

(11)

2.3 Silicon Area

33

(2)

2.4 Delay Estimation

35

(9)

2.5 Power Dissipation

44

(5)

2.6 Exercises

49

(6)

3 Implementation of Fundamental Operations

55

(98)

3.1 Numeric Representations

55

(9)

3.2 Adders and Subtractors

64

(30)

3.2.1 Basic adder circuits

64

(6)

3.2.2 Adders with fast carry chain

70

(5)

3.2.3 Adders with parallel carry computation

75

(3)

3.2.4 Hierarchical adder structures

78

(11)

3.2.5 Subtractors

89

(2)

3.2.6 Carry save adders

91

(3)

3.3 Multipliers

94

(25)

3.3.1 Multipliers for positive numbers

94

(14)

3.3.2 Signed number multipliers

108

(11)

3.4 Dividers

119

(10)

3.4.1 Binary division algorithms

120

(3)

3.4.2 Array dividers

123

(6)

3.5 Implementations of Elementary Functions

129

(20)

3.5.1 Methods of computing elementary functions

129

(6)

3.5.2 The CORDIC method

135

(14)

3.6 Exercises

149

(4)

4 Measures for Increasing Performance

153

(34)

4.1 Parallel Processing and Pipelining

153

(11)

4.2 Assessment of the Architecture Alternatives

164

(20)

4.2.1 Architecture efficiency

166

(10)

4.2.2 A comparison of power dissipation

176

(3)

4.2.3 Multicriteria assessment

179

(5)

4.3 Exercises

184

(3)

5 Array Processor Architectures

187

(58)

5.1 Implementations of Array Processors

188

(3)

5.2 Algorithmic Representations

191

(10)

5.3 Linear Mapping Methods

201

(25)

5.3.1 Estimating the number of PEs

203

(2)

5.3.2 Mapping without changing the number of nodes

205

(3)

5.3.3 Mapping with a reduced number of nodes

208

(5)

5.3.4 Formal description of the projection method

213

(8)

5.3.5 Multiprojection

221

(5)

5.4 Extensions of the Mapping Methods

226

(11)

5.4.1 Partitioning

226

(7)

5.4.2 Projection of nodes with different operations

233

(4)

5.5 Implementation Aspects and Optimization

237

(3)

5.6 Exercises

240

(5)

6 Filter Structures

245

(42)

6.1 Characterization of Digital Filters

245

(4)

6.2 1-D FIR Filter Structures

249

(14)

6.2.1 Signal flow graph of a 1-D FIR filter

249

(2)

6.2.2 Implementations for low throughput

251

(2)

6.2.3 Implementations for high throughput

253

(10)

6.3 2-D FIR Filters

263

(2)

6.4 Polyphase Filter Structures

265

(9)

6.4.1 Decimation filters

266

(2)

6.4.2 Interpolation filters

268

(2)

6.4.3 Filter banks

270

(4)

6.5 IIR Filter Structures

274

(9)

6.5.1 Recursive filters in direct form

274

(2)

6.5.2 MSB first arithmetic

276

(5)

6.5.3 Lookahead technique

281

(2)

6.6 Exercises

283

(4)

7 Implementations of the Discrete Fourier Transform

287

(18)

7.1 Characteristics of the DFT

287

(2)

7.2 Direct Implementation of the DFT

289

(4)

7.3 Fast Fourier Transforms

293

(10)

7.4 Exercises

303

(2)

8 Programmable Digital Signal Processors

305

(52)

8.1 The Architectures of DSP Processors

306

(23)

8.1.1 The architecture of standard computers

306

(6)

8.1.2 Architectural approaches for DSP processors

312

(11)

8.1.3 Characteristics of available DSPs

323

(6)

8.2 The Programming of Signal Processing Algorithms

329

(7)

8.2.1 An FIR filter program

329

(4)

8.2.2 A DFT program

333

(3)

8.3 Architecture Optimization via Simple Models

336

(10)

8.3.1 Instruction pipelining

336

(4)

8.3.2 Special arithmetic modules

340

(3)

8.3.3 On-chip memory

343

(2)

8.3.4 Software measurement

345

(1)

8.4 Data Path Synthesis

346

(6)

8.5 Design Support for DSP Systems

352

(1)

8.6 Exercises

353

(4)

9 Multiprocessor Systems

357

(24)

9.1 Architectures of Multiprocessors

357

(12)

9.2 Performance Comparison of Multiprocessor Structures

369

(8)

9.3 Exercises

377

(4)

10 Implementation Strategies

381

(20)

10.1 Algorithm-Dependent Architecture Modifications

382

(9)

10.2 Implementation Alternatives

391

(7)

10.3 Exercises

398

(3)

References

401

(10)

Index

411

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Architectures for Digital Signal Processing

Summary

Author Biography

Table of Contents

Supplemental Materials