ARM System Developer's Guide

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ISBN: 9781558608740 | 1558608745
Cover: Hardcover
Copyright: 3/25/2004

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Over the last ten years, the ARM architecture has become the most pervasive 32-bit architecture in the world. In this new developer's guide, the authors provide a comprehensive text describing the operation of the ARM core from a product developer's perspective with a clear emphasis on software. The book demonstrates not only how to write efficient ARM software in C and assembler but also how to optimize code.

ABOUT THE AUTHORS

PREFACE

CHAPTER 1 ARM EMBEDDED SYSTEMS

(16)

1.1 The RISC Design Philosophy

(1)

1.2 The ARM Design Philosophy

(1)

1.3 Embedded System Hardware

(6)

1.4 Embedded System Software

(3)

1.5 Summary

(4)

CHAPTER 2 ARM PROCESSOR FUNDAMENTALS

(28)

2.1 Registers

(1)

2.2 Current Program Status Register

(7)

2.3 Pipeline

(4)

2.4 Exceptions, Interrupts, and the Vector Table

(1)

2.5 Core Extensions

(3)

2.6 Architecture Revisions

(1)

2.7 ARM Processor Families

(5)

2.8 Summary

(4)

CHAPTER 3 INTRODUCTION TO THE ARM INSTRUCTION SET

(40)

3.1 Data Processing Instructions

(8)

3.2 Branch Instructions

(2)

3.3 Load-Store Instructions

(13)

3.4 Software Interrupt Instruction

(2)

3.5 Program Status Register Instructions

(3)

3.6 Loading Constants

(1)

3.7 ARMv5E Extensions

(3)

3.8 Conditional Execution

(2)

3.9 Summary

(3)

CHAPTER 4 INTRODUCTION TO THE THUMB INSTRUCTION SET

(16)

4.1 Thumb Register Usage

(1)

4.2 ARM-Thumb Interworking

(2)

4.3 Other Branch Instructions

(1)

4.4 Data Processing Instructions

(3)

4.5 Single-Register Load-Store Instructions

(1)

4.6 Multiple-Register Load-Store Instructions

(1)

4.7 Stack Instructions

(1)

4.8 Software Interrupt Instruction

(1)

4.9 Summary

100

(3)

CHAPTER 5 EFFICIENT C PROGRAMMING

103

(54)

5.1 Overview of C Compilers and Optimization

104

(1)

5.2 Basic C Data Types

105

(8)

5.3 C Looping Structures

113

(7)

5.4 Register Allocation

120

(2)

5.5 Function Calls

122

(5)

5.6 Pointer Aliasing

127

(3)

5.7 Structure Arrangement

130

(3)

5.8 Bit-fields

133

(3)

5.9 Unaligned Data and Endianness

136

(4)

5.10 Division

140

(9)

5.11 Floating Point

149

(1)

5.12 Inline Functions and Inline Assembly

149

(4)

5.13 Portability Issues

153

(2)

5.14 Summary

155

(2)

CHAPTER 6 WRITING AND OPTIMIZING ARM ASSEMBLY CODE

157

(50)

6.1 Writing Assembly Code

158

(5)

6.2 Profiling and Cycle Counting

163

(1)

6.3 Instruction Scheduling

163

(8)

6.4 Register Allocation

171

(9)

6.5 Conditional Execution

180

(3)

6.6 Looping Constructs

183

(8)

6.7 Bit Manipulation

191

(6)

6.8 Efficient Switches

197

(4)

6.9 Handling Unaligned Data

201

(3)

6.10 Summary

204

(3)

CHAPTER 7 OPTIMIZED PRIMITIVES

207

(52)

7.1 Double-Precision Integer Multiplication

208

(4)

7.2 Integer Normalization and Count Leading Zeros

212

(4)

7.3 Division

216

(22)

7.4 Square Roots

238

(3)

7.5 Transcendental Functions: log, exp, sin, cos

241

(7)

7.6 Endian Reversal and Bit Operations

248

(5)

7.7 Saturated and Rounded Arithmetic

253

(2)

7.8 Random Number Generation

255

(1)

7.9 Summary

256

(3)

CHAPTER 8 DIGITAL SIGNAL PROCESSING

259

(58)

8.1 Representing a Digital Signal

260

(9)

8.2 Introduction to DSP on the ARM

269

(11)

8.3 FIR filters

280

(14)

8.4 IIR Filters

294

(9)

8.5 The Discrete Fourier Transform

303

(11)

8.6 Summary

314

(3)

CHAPTER 9 EXCEPTION AND INTERRUPT HANDLING

317

(50)

9.1 Exception Handling

318

(6)

9.2 Interrupts

324

(9)

9.3 Interrupt Handling Schemes

333

(31)

9.4 Summary

364

(3)

CHAPTER 10 FIRMWARE

367

(14)

10.1 Firmware and Bootloader

367

(5)

10.2 Example: Sandstone

372

(7)

10.3 Summary

379

(2)

CHAPTER 11 EMBEDDED OPERATING SYSTEMS

381

(22)

11.1 Fundamental Components

381

(2)

11.2 Example: Simple Little Operating System

383

(17)

11.3 Summary

400

(3)

CHAPTER 12 CACHES

403

(58)

12.1 The Memory Hierarchy and Cache Memory

404

(4)

12.2 Cache Architecture

408

(10)

12.3 Cache Policy

418

(5)

12.4 Coprocessor 15 and Caches

423

(1)

12.5 Flushing and Cleaning Cache Memory

423

(20)

12.6 Cache Lockdown

443

(13)

12.7 Caches and Software Performance

456

(1)

12.8 Summary

457

(4)

CHAPTER 13 MEMORY PROTECTION UNITS

461

(30)

13.1 Protected Regions

463

(2)

13.2 Initializing the MPU, Caches, and Write Buffer

465

(13)

13.3 Demonstration of an MPU system

478

(9)

13.4 Summary

487

(4)

CHAPTER 14 MEMORY MANAGEMENT UNITS

491

(58)

14.1 Moving from an MPU to an MMU

492

(1)

14.2 How Virtual Memory Works

493

(8)

14.3 Details of the ARM MMU

501

(1)

14.4 Page Tables

501

(5)

14.5 The Translation Lookaside Buffer

506

(4)

14.6 Domains and Memory Access Permission

510

(2)

14.7 The Caches and Write Buffer

512

(1)

14.8 Coprocessor 15 and MMU Configuration

513

(2)

14.9 The Fast Context Switch Extension

515

(5)

14.10 Demonstration: A Small Virtual Memory System

520

(25)

14.11 The Demonstration as mmuSLOS

545

(1)

14.12 Summary

545

(4)

CHAPTER 15 THE FUTURE OF THE ARCHITECTURE BY JOHN RAYFIELD

549

(20)

15.1 Advanced DSP and SIMD Support in ARMv6

550

(10)

15.2 System and Multiprocessor Support Additions to ARMv6

560

(3)

15.3 ARMv6 Implementations

563

(1)

15.4 Future Technologies beyond ARMv6

563

(3)

15.5 Summary

566

(3)

APPENDIX A ARM AND THUMB ASSEMBLER INSTRUCTIONS

569

(68)

A.1 Using This Appendix

569

(1)

A.2 Syntax

570

(3)

A.3 Alphabetical List of ARM and Thumb Instructions

573

(47)

A.4 ARM Assembler Quick Reference

620

(11)

A.5 GNU Assembler Quick Reference

631

(6)

APPENDIX B ARM AND THUMB INSTRUCTION ENCODINGS

637

(10)

B.1 ARM Instruction Set Encodings

637

(1)

B.2 Thumb Instruction Set Encodings

638

(7)

B.3 Program Status Registers

645

(2)

APPENDIX C PROCESSORS AND ARCHITECTURE

647

(4)

C.1 ARM Naming Convention

647

(1)

C.2 Core and Architectures

647

(4)

APPENDIX D INSTRUCTION CYCLE TIMINGS

651

(16)

D.1 Using the Instruction Cycle Timing Tables

651

(2)

D.2 ARM7TDMI Instruction Cycle Timings

653

(1)

D.3 ARM9TDMI Instruction Cycle Timings

654

(1)

D.4 StrongARM1 Instruction Cycle Timings

655

(1)

D.5 ARM9E Instruction Cycle Timings

656

(2)

D.6 ARM10E Instruction Cycle Timings

658

(1)

D.7 Intel XScale Instruction Cycle Timings

659

(2)

D.8 ARM11 Cycle Timings

661

(6)

APPENDIX E SUGGESTED REAPING

667

(2)

E.1 ARM References

667

(1)

E.2 Algorithm References

667

(1)

E.3 Memory Management and Cache Architecture (Hardware Overview and Reference)

667

(1)

E.4 Operating System References

668

(1)

INDEX

669

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ARM System Developer's Guide

Summary

Table of Contents

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