Basics of CMOS Cell Design

Market: electronic circuit designers and electronic engineering students CD-ROM contains circuit simulation tools that can be used to work the many examples presented in the text Covers MOS devices and technology, MOS modeling, the inverter, basic gates, analog cells, and more

Dr. Etienne Sicard is Professor of Electronic Engineering at the ISNA Electronic Engineering School of Toulouse. He has taught at the University of Balearic Islands, Spain, and the University of Osaka, Japan. He is the author of several educational software packages in microelectronics and sound processing.

Dr. Sonia Delmas Bendhia is a Senior Lecturer in the Department of Electrical and Computer Engineering at the INSA Electronic Engineering School of Toulouse.

Preface	p. vii
Acknowledgments	p. ix
Abbreviations and Symbols	p. xv
Introduction	p. 1
General Trends	p. 1
The Device Scale Down	p. 5
Frequency Improvements	p. 5
Layers	p. 6
Density	p. 8
Design Trends	p. 10
Market	p. 11
Conclusion	p. 11
References	p. 11
Exercises	p. 12
The MOS Devices and Technology	p. 13
Properties of Silicon	p. 13
N-type and P-type Silicon	p. 16
Silicon Dioxide	p. 18
Metal Materials	p. 19
The MOS Switch	p. 20
The MOS Aspect	p. 23
MOS Layout	p. 25
Dynamic MOS Behaviour	p. 32
The Perfect Switch	p. 38
Layout Considerations	p. 41
CMOS Process	p. 44
Conclusion	p. 48
References	p. 48
Exercises	p. 48
The MOS Modelling	p. 51
Introduction to Modelling	p. 51
MOS Model 1	p. 53
MOS Model 3	p. 57
The BSIM4 MOS Model	p. 66
Specific MOS Devices	p. 80
Process Variations	p. 87
Concluding Remarks	p. 90
References	p. 91
Exercises	p. 91
The Inverter	p. 93
Logic Symbol	p. 93
CMOS Inverter	p. 94
Inverter Layout	p. 95
Inverter Simulation	p. 104
Power Consumption	p. 111
Static Characteristics	p. 114
Random Simulation	p. 118
The Inverter as a Library Cell	p. 120
3-State Inverter	p. 122
All nMOS Inverters	p. 125
Ring Oscillator	p. 127
Latch-up Effect	p. 133
Conclusion	p. 134
References	p. 134
Exercises	p. 135
Interconnects	p. 137
Introduction	p. 137
Metal Layers	p. 137
Contact and Vias	p. 139
Design Rules	p. 142
Capacitance Associated with Interconnects	p. 146
Resistance Associated with Interconnects	p. 153
Signal Transport	p. 157
Improved Signal Transport	p. 164
Repeaters for Improved Signal Transport	p. 167
Crosstalk Effects in Interconnects	p. 169
Antenna Effect	p. 173
Inductance	p. 176
Conclusion	p. 179
References	p. 179
Exercises	p. 180
Basic Gates	p. 182
Introduction	p. 182
Combinational Logic	p. 182
CMOS Logic Gate Concept	p. 184
The NAND Gate	p. 185
The AND Gate	p. 202
The NOR Gate	p. 204
The OR Gate	p. 207
The XOR Gate	p. 208
Complex Gates	p. 214
Multiplexor	p. 218
Shifters	p. 227
Description of Basic Gates in Verilog	p. 229
Conclusion	p. 231
References	p. 231
Exercises	p. 231
Arithmetics	p. 233
Data Formats	p. 233
The Adder Circuit	p. 236
Adder Cell Design	p. 238
Ripple-carry Adder	p. 247
Signed Adder	p. 253
Fast Adder Circuits	p. 254
Substractor Circuit	p. 258
Comparator Circuit	p. 260
Student Project: A Decimal Adder	p. 262
Multiplier	p. 267
Conclusion	p. 272
References	p. 272
Exercises	p. 273
Sequential Cell Design	p. 274
The Elementary Latch	p. 274
RS Latch	p. 275
D Latch	p. 282
Edge-trigged D Register	p. 288
Clock Divider	p. 295
Synchronous Counters	p. 299
Shift Registers	p. 301
A 24-hour Clock	p. 303
Conclusion	p. 307
References	p. 307
Exercises	p. 307
Analog Cells	p. 309
Resistor	p. 309
Capacitor	p. 314
The MOS Device for Analog Design	p. 321
Diode-connected MOS	p. 324
Voltage Reference	p. 326
Current Mirror	p. 331
The MOS Transconductance	p. 335
Single Stage Amplifier	p. 336
Simple Differential Amplifier	p. 345
Wide Range Amplifier	p. 354
On-chip Voltage Regulator	p. 357
Noise	p. 359
Conclusion	p. 361
References	p. 361
Exercises	p. 361
Conclusion	p. 363
Appendices
Design Rules	p. 364
Lambda Units	p. 364
Layout Design Rules	p. 365
Pads	p. 368
Electrical Extraction Principles	p. 368
Node Capacitance Extraction	p. 369
Resistance Extraction	p. 372
Simulation Parameters	p. 373
Technology Files for Dsch	p. 376
Microwind Program Operation and Commands	p. 378
Getting Started	p. 378
List of Commands in Microwind	p. 379
Dsch Logic Editor Operation and Commands	p. 403
Getting Started	p. 403
Commands	p. 403
Quick Reference Sheet	p. 413
Microwind Menus	p. 413
Microwind Simulation Menu	p. 416
Dsch Menus	p. 417
List of Files	p. 419
List of Measurement Files	p. 419
Glossary	p. 422
Index	p. 424
Software Download Information	p. 428
Authors' Profiles	p. 429
Table of Contents provided by Ingram. All Rights Reserved.

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Basics of CMOS Cell Design

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