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Item Detail

A Vhdl Synthesis Primer

Author(s): Bhasker, Jayaram

ISBN10: 0965039102

ISBN13: 9780965039109

Cover: Hardcover

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A must primer for anyone who is beginning to learn synthesis using VHDL. Learn to model for synthesis using VHDL. Details inside.

Preface

Chapter 1 Language Basics

(13)

1.1 About VHDL

(1)

1.2 Design units

(2)

1.3 Data objects

(1)

1.4 Data types

(1)

1.5 Design description

(4)

1.6 Design libraries

(1)

1.7 Simulating a model

(1)

1.8 Synthesizing a model

(2)

Chapter 2 Synthesis Basics

(20)

2.1 What is synthesis?

(1)

2.2 Synthesis in a design process

(2)

2.3 Value holders for hardware modeling

(3)

2.4 Logic value system

(1)

2.5 Computing bit-widths

(10)

2.5.1 Integer types

(1)

2.5.2 Type BIT_VECTOR

(1)

2.5.3 Enumeration types

(2)

2.5.4 Encoding metalogical values

(4)

2.5.5 Array types

(1)

2.5.6 Signed and unsigned types

(2)

2.6 Resolution functions

(2)

Chapter 3 Mapping Statements to Gates

(64)

3.1 Assignment statement

(2)

3.2 Logical operators

(2)

3.3 Arithmetic operators

(3)

3.3.1 Unsigned arithmetic

(1)

3.3.2 Signed arithmetic

(1)

3.3.3 Computing result size

(1)

3.3.4 Modeling a carry

(1)

3.4 Relational operators

(1)

3.5 Vectors and slices

(4)

3.5.1 Constant index

(2)

3.5.2 Non-constant index

(2)

3.6 Process statement

(3)

3.7 If statement

(6)

3.7.1. Inferring latches from if statements

(4)

3.8 Case statement

(5)

3.8.1 Inferring latches from case statements

(2)

3.9 Loop statement

(1)

3.10 Null statement

(1)

3.11 Wait statement

(4)

3.12 Modeling flip-flops

(10)

3.12.1. Multiple clocks

(1)

3.12.2. Multi-phase clocks

(1)

3.12.3. With asynchronous preset and clear

(3)

3.12.4. With synchronous preset and clear

(2)

3.13 Modeling latches

(1)

3.14 Other forms of signal assignment

(5)

3.14.1. Conditional signal assignment statement

(2)

3.14.2. Selected signal assignment statement

(1)

3.14.3. Sequential signal assignment statement

(2)

3.15. Functions

(2)

3.16. Procedures

(3)

3.17. Records

(1)

3.18. Block statement

(2)

3.19. Using metalogical values

(2)

3.19.1. The don't-care value (D)

(1)

3.19.2. The unknown value (U)

(1)

3.19.3. The high-impedance value (Z)

(1)

3.20. Component instantiation statement

(1)

3.21. Using predefined blocks

(2)

3.22. Generics

(3)

3.23. Generate statement

(2)

Chapter 4 Model Optimizations

(18)

4.1. Resource allocation

(3)

4.2. Conversion functions

101

(1)

4.3. Type INTEGER

102

(1)

4.4. Common subexpressions

103

(1)

4.5. Moving code

104

(1)

4.6. Common factoring

105

(1)

4.7. Commutativity and associativity

106

(1)

4.8. Other optimizations

107

(1)

4.9. Flip-flop and latch optimizations

108

(2)

4.9.1. Avoiding flip-flops

108

(1)

4.9.2. Avoiding latches

109

(1)

4.10. Design size

110

(1)

4.11. Using parenthesis

111

(1)

4.12. Building with predefined blocks

112

(3)

Chapter 5 Verification

115

(20)

5.1. Entity interface

116

(1)

5.2. A test bench

117

(4)

5.3. Delays in assignment statements

121

(1)

5.4. Unconnected ports

122

(2)

5.5. Signals vs. variables

124

(1)

5.6. Inertial and transport delays

125

(1)

5.7. Resolution function

126

(1)

5.8. Built-in types and functions

127

(1)

5.9. Sensitivity list

127

(2)

5.10. Initialization

129

(4)

5.11. Using attribute ENUM_TYPE_ENCODING

133

(2)

Chapter 6 Modeling Hardware Elements for Synthesis

135

(72)

6.1. Modeling a Wire

136

(2)

6.2. Modeling combinational logic

138

(1)

6.3. Modeling synchronous logic

139

(2)

6.4. Modeling a flip-flop

141

(2)

6.4.1. From a signal

141

(1)

6.4.2. From a variable

142

(1)

6.5 Flip-flop with asynchronous preset and clear

143

(2)

6.6. Flip-flop with synchronous preset and clear

145

(2)

6.7. Modeling a latch

147

(2)

6.8. Latch with asynchronous preset and clear

149

(2)

6.9. Modeling a memory

151

(1)

6.10. Using a pre-built component

152

(1)

6.11. Writing boolean equations

153

(2)

6.12. Modeling a finite state machine

155

(8)

6.12.1. Moore FSM

155

(2)

6.12.2. Mealy FSM

157

(2)

6.12.3. Encoding states

159

(4)

6.13. Modeling an universal shift register

163

(1)

6.14. Modeling an ALU

164

(5)

6.14.1. A generic ALU

164

(3)

6.14.2. A simple ALU

167

(2)

6.15. Modeling a counter

169

(6)

6.15.1. Ripple counter

169

(1)

6.15.2. Modulo-N counter

170

(2)

6.15.3. Johnson counter

172

(1)

6.15.4. Gray counter

173

(2)

6.16. Modeling a generic adder

175

(1)

6.17. Modeling a generic comparator

176

(1)

6.18. Modeling a generic decoder

177

(4)

6.18.1. A simple decoder

177

(2)

6.18.2. Binary decoder

179

(1)

6.18.3. Johnson decoder

180

(1)

6.19. Modeling a multiplexer

181

(4)

6.19.1. A simple multiplexer

181

(2)

6.19.2. A generic multiplexer

183

(2)

6.20. Modeling a generic parity circuit

185

(1)

6.21. Modeling a tri-state gate

186

(1)

6.22. A count three 1's model

187

(4)

6.23. A factorial model

191

(2)

6.24. A UART model

193

(10)

6.25. A blackjack model

203

(4)

Appendix A Synthesizable Constructs

207

(10)

Appendix B An Arithmetic Package

217

(6)

Appendix C A Generic Library

223

(8)

Bibliography

231

(4)

Index

235

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