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A SystemC Primer

Author(s): Bhasker, J.
Edition: 2nd w/ CD-
ISBN10: 0965039129
ISBN13: 9780965039123
Cover: Hardcover
 
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Table of Contents
Foreword xiii
Preface xxi
Introduction
1(14)
What is SystemC?
1(2)
Why SystemC?
3(3)
Design Methodology
6(4)
Capabilities
10(2)
SystemC RTL
12(1)
Book Organization
12(1)
Exercises
13(2)
Getting Started
15(16)
Basics
15(3)
Another Example
18(3)
Describing Hierarchy
21(3)
Verifying the Functionality
24(5)
Exercises
29(2)
Data Types
31(32)
Value Holders
31(2)
Summary of Types
33(2)
Bit Type
35(1)
Arbitrary Width Bit Type
36(4)
Logic Type
40(3)
Arbitrary Width Logic Type
43(5)
Signed Integer Type
48(6)
Unsigned Integer Type
54(1)
Arbitrary Precision Signed Integer Type
55(1)
Arbitrary Precision Unsigned Integer Type
56(1)
Resolved Types
57(1)
User-defined Data Types
58(2)
Recommended Data Types
60(1)
Exercises
61(2)
Modeling Combinational Logic
63(40)
SC_MODULE
63(4)
File Structure
65(2)
An Example
67(2)
Reading and Writing Ports and Signals
69(1)
Logical Operators
70(2)
Arithmetic Operators
72(4)
Unsigned Arithmetic
73(1)
Signed Arithmetic
74(2)
Relational Operators
76(3)
Vectors and Ranges
79(5)
Constant Index
79(2)
Non-constant Index
81(3)
If Statement
84(4)
Switch Statement
88(4)
Loops
92(2)
Methods
94(4)
Structures
98(2)
Multiple Processes and Delta Delay
100(1)
Summary
101(1)
Exercises
102(1)
Modeling Synchronous Logic
103(24)
Modeling Flip-flops
104(2)
Multiple Processes
106(2)
Flip-flop with Asynchronous Preset and Clear
108(5)
Flip-flop with Synchronous Preset and Clear
113(1)
Multiple and Multi-phase Clocks
114(3)
Modeling Latches
117(8)
If Statement
117(4)
Switch Statement
121(1)
Avoiding Latches
122(3)
Summary
125(1)
Exercises
125(2)
Miscellaneous Logic
127(26)
Three-state Drivers
127(6)
Multiple Drivers
133(3)
Handling Don't-cares
136(2)
Hierarchy
138(8)
Parameterizing Modules
146(3)
Variable and Signal Assignments
149(2)
Exercises
151(2)
Modeling Examples
153(28)
Parameterizable Register with Three-state Output
153(3)
A Memory Model
156(2)
Modeling an FSM
158(8)
Moore FSM
158(4)
Mealy FSM
162(4)
Universal Shift Register
166(2)
Counters
168(7)
Modulo-N Counter
168(3)
Johnson Counter
171(1)
Gray Code Up-down Counter
172(3)
Johnson Decoder
175(1)
A Factorial Model
176(2)
Modeling a ROM
178(2)
Exercises
180(1)
Writing Testbenches
181(52)
Writing a Testbench
182(3)
Simulation Control
185(7)
sc_clock
185(1)
sc_trace
186(2)
sc_start
188(1)
sc_stop
189(1)
sc_time_stamp
189(1)
sc_simulation_time
189(1)
sc_cycle and sc_initialize
190(1)
sc_time
190(2)
Waveforms
192(15)
Arbitrary Waveform
192(2)
Complex Repetitive Waveform
194(1)
Generating a Derived Clock
195(2)
Reading Stimuli from Files
197(6)
Reactive Stimuli
203(4)
Monitoring Behavior
207(3)
Asserting Valid Behavior
207(2)
Dumping Results into a Text File
209(1)
More Examples
210(16)
Flip-flop
210(6)
Multiplexer with Synchronous Output
216(4)
Full Adder
220(4)
Cycle-level Simulation
224(2)
Statement Ordering within sc_main
226(1)
Tracing Aggregate Types
227(2)
Tracing Enumeration Types
229(1)
Exercises
230(3)
Modeling Beyond RTL
233(36)
SC_THREAD Process
234(5)
Dynamic Sensitivity
239(5)
Constructor Arguments
244(6)
More Examples
250(2)
Greatest Common Divisor
250(1)
Filter
251(1)
Ports, Interfaces and Channels
252(6)
Advanced Topics
258(7)
Shared Data Members
258(1)
Fixed Point Types
259(1)
Module
259(1)
Other Methods
260(5)
Simulation Algorithm
265(1)
Exercises
266(3)
Appendix A Runtime Environment
269(6)
Software Installation
269(1)
Compiling your Design
270(2)
Simulating your Design
272(1)
Debugging
272(3)
Appendix B SystemC RTL: A Synthesizable Subset
275(8)
SystemC Features
276(2)
C++ Features
278(5)
Bibliography 283(2)
Index 285

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