ESD Failure Mechanisms and Models

This book presents information on electrostatic discharge (ESD) failure mechanisms, spanning a range of technologies from early CMOS applications to future CMOS concepts. Voldman uses his wealth of experience in the field of ESD to address failure mechanisms associated with each CMOS generation, including those applicable to electrical overstress (EOS) and latchup. He also provides the processes or circuit solutions for eliminating failure defects, giving practical examples of failure mechanisms and the working applications they can effect. The book opens with an exposition of the historical trends behind ESD, including how technology scaling has affected the ESD failure mechanisms, and potential developments of the technology. The book goes on to examine different failure models and analysis tools, before applying this to CMOS technology; past, present and future developments, SOI technology, RF CMOS and RF MEMS. The final chapters of the book cover bipolar technology failures, Gallium Arsenide failure mechanisms and devices and magnetic recording failure mechanisms. Provides a comprehensive analysis of ESD failure mechanisms over a wide range of semiconductor materials, devices, circuits and applications. Sets out methods for eliminating failure mechanisms through workable circuit solutions, including practical examples of failure defects. Discusses established and contemporary technologies, as well as emerging and future trends such as RF complementary metal-oxide semiconductor (CMOS) and digital applications, carbon nanotubes (CNTs), local oxidization of silicon (LOCOS)-based CMOS, STI-based CMOS, multi-gate devices (MUGFETs) and FinFET transistors. Addresses the historical trends in ESD failure mechanisms, including how ESD failure practice is used to design and improve semiconductor chips, and how technology scaling has affected this.

Dr Steven H. Voldman received his B.S. in Engineering Science from the University of Buffalo (1979); M.S. EE (1981) and Electrical Engineer Degree (1982) from M.I.T; MS Engineering Physics (1986) and Ph.D EE (1991) from the University of Vermont under IBM's Resident Study Fellow Program. At M.I.T, he worked as a member of the M.I.T. Plasma Fusion Center, and the High Voltage Research Laboratory (HVRL). At IBM, as a reliability device engineer, his work include pioneering work in bipolar/ CMOS SRAM alpha particle and cosmic ray SER simulation, MOSFET gate-induced drain leakage (GIDL) mechanism, hot electron, epitaxy/well design, CMOS latchup, and ESD. Since 1986, he has been responsible for defining the IBM ESD/latchup strategy for CMOS, SOI, BiCMOS and RF CMOS and SiGe technologies. He has authored ESD and latchup publications in the area of MOSFET Scaling, device simulations, copper, low-k, MR heads, CMOS, SOI , Sage and SiGeC technology. Voldman served as SEMATECH ESD Working Group Chairman (1996-2000), ESD Association General Chairman and Board of Directors, International Reliability Physics (IRPS) ESD/Latchup Chairman, International Physical and Failure Analysis (IPFA) Symposium ESD Sub-Committee Chairman, ESD Association Standard Development Chairman on Transmission Line Pulse Testing, ESD Education Committee, and serves on the ISQED Committee, Taiwan ED Conference (T-ESDC) Technical Program Committee. Voldman has provided ESD lectures for universities (e.g. MIT Lecture Series, Taiwan National Chiao-Tung University, and Singapore Nanyang Technical University). He is a recipient of over 125 US patents, over 100 publications, and also provides talks on patenting, and invention. He has been featured in EE Times, Intellectual Property Law and Business and authored the first article on ESD phenomena for the October 2002 edition of Scientific American entitled Lightening Rods for Nanostructures, and Pour La Science, Le Scienze, and Swiat Nauk international editions. Dr. Voldman was recently accepted as the first IEEE Fellow for ESD phenomena in semiconductors for ' contributions to electrostatic discharge protection CMOS, SOI and SiGe technologies'.