High Performance Memories New Architecture DRAMs and SRAMs - Evolution and Function

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ISBN: 9780471986102 | 0471986100
Cover: Hardcover
Copyright: 8/3/1999

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High Performance Memories New architecture DRAMs and SRAMs evolution and function Revised Edition Betty Prince Memory Strategies International, Leander, Texas, USA Now presenting extra product specific material on the new DDR SDRAMs, ESDRAMs and DDR ESDRAMs, Direct Rambus DRAMs, SLDRAM, VCDRAM, SGRAM and DDR SGRAM, and DP-DRAM. Fully updated to incorporate the latest industry achievements in this fast-moving field, High Performance Memories, Revised provides an overview of the issues involved in advanced memory design. Drawing on her work at the cutting edge of memory technology, Prince surveys the latest trends in development and assesses the range of memory devices and systems available. New features include: * Examination of the latest DRAMs standards * Discussion of electrical characteristics of high speed memories including SSTL interfaces and techniques in the testing of fast RAMS * Coverage of the effect of packaging on memory speed, encompassing DDR DRAM, DR-DRAM and SLDRAM Written by an internationally respected author, this comprehensively revised edition will be a boon to practising engineers involved in the design and manufacture of high speed systems and semiconductor memories. Advanced students of electrical engineering and researchers in computing and telecommunications will find High Performance Memories, Revised an invaluable reference.

Acknowledgments

(2)

About the author

xiii

(2)

Introduction

1 Overview of High Speed Memories and Memory Systems

(12)

1.1 Overview of Fast Memory Trends

(2)

1.2 New Memory Architectures to Improve Bandwidth

(3)

1.3 Memories in Computer Systems

(5)

1.3.1 Cache SRAMs

(2)

1.3.2 DRAMs in High Performance Main Memory

(1)

1.3.3 DRAMs in Graphics Subsystems

(1)

1.4 Effect of Electrical System Characteristics on Speed

(1)

1.5 Effect of Packaging on Speed

(1)

Bibliography

(1)

2 High Performance Memory Applications

(24)

2.1 The Concept of a High Performance Memory

(1)

2.2 System Architecture Determines Performance

(1)

2.3 Systems Applications for High Performance SRAMs

(8)

2.3.1 Overview of Fast SRAM Applications

(2)

2.3.2 Systems with Fast Caches

(1)

2.3.3 Synchronous and Asynchronous SRAMs in Fast Caches

(2)

2.3.4 Cache Size and Speed Requirements of Computer Systems

(2)

2.3.5 SRAM Use Based on Processor Speed

(1)

2.4 Overview of Applications for High Performance DRAMs

(1)

2.5 Main Memory Applications for DRAMs

(4)

2.5.1 Mainframe and Supercomputer Applications

(1)

2.5.2 DRAMs in Main Memory in Workstations

(1)

2.5.3 DRAMs in Main Memory in PCs

(1)

2.5.4 DRAMs in Add-On Modules for Main Memory

(1)

2.6 DRAMs in Graphic Subsystems

(6)

2.6.1 Television Displays

(1)

2.6.2 DRAMs in Television Related Applications

(1)

2.6.3 Graphics DRAMs in Computer Graphics Subsystems

(5)

2.6.4 Frame Buffer Operations to Improve System Bandwidth

(1)

2.7 Peripheral Applications for DRAMs

(1)

2.7.1 Printers

(1)

2.8 Consumer Applications for Fast DRAMs

(1)

2.8.1 Fast DRAMs in Consumer Games

(1)

2.9 Communications Applications for DRAMs

(1)

2.9.1 Digital Switching Systems

(1)

2.10 Emerging Communications Applications

(2)

2.10.1 Video Conferencing and Interactive TV Equipment

(1)

2.10.2 ATM Switches

(1)

2.10.3 Digital Compression

(1)

2.10.4 Mobile Communications

(1)

2.11 Industrial Applications for DRAMs

(1)

2.11.1 Medical Systems

(1)

2.11.2 Embedded Controllers

(1)

Bibliography

(1)

3 Fast SRAMs

(30)

3.1 Overview of Fast SRAMs

(1)

3.2 Fast SRAM Technology

(2)

3.3 Architectural Influence on SRAM Speed

(5)

3.3.1 Separate and Common Inputs and Outputs

(3)

3.3.2 Output Enable

(1)

3.3.3 Wide Bus SRAMs for Bandwidth Improvement

(2)

3.4 Fast Technologies

(2)

3.4.1 BiCMOS Technology for Speed

(1)

3.4.2 GaAs Technology for Speed

(1)

3.5 Effect of Lower Power Supply Voltage on Speed

(1)

3.6 Effect of Temperature on Speed

(1)

3.7 Revolutionary Pinout for Speed

(2)

3.7.1 Revolutionary Interface on ECL SRAMs

(1)

3.8 Latched and Registered SRAMs

(13)

3.8.1 Overview

(1)

3.8.2 Latches

(3)

3.8.3 Registers

(5)

3.8.4 Synchronous (Registered) SRAM with Separate I/O Option

(1)

3.8.5 Fast SRAMs with Early Write Feature, Zero Bus Turnaround

(3)

3.8.6 Double Data Rate Synchronous SRAMs

(1)

3.9 FIFOs

(3)

3.10 Fast Non-volatile Memories

(1)

Bibliography

(2)

4 Fast Cache Memory

(30)

4.1 Overview

(1)

4.2 Cache Concept and Theory

(4)

4.2.1 The Problem

(1)

4.2.2 Supplying Data from DRAM Main Memory

(1)

4.2.3 Supplying Data from a Cache Hierarchy

(1)

4.3 Effective Speed of the Cache Hierarchy

(1)

4.4 First Level Cache

(1)

4.5 Limitations in Size of an L1 Cache

(1)

4.6 Increasing the Hit Rate of the Cache: Cache Theory

(1)

4.6.1 Simple Cache Theory

(1)

4.7 Cache Architecture

(2)

4.7.1 Principles of Locality of Time and Space

(1)

4.8 Data and Instruction Caches

(1)

4.9 Cache Associativity

(3)

4.9.1 Direct Mapped Cache

(1)

4.9.2 N-Way Set Associative Cache

(1)

4.9.3 Content Addressable Memory

(2)

4.10 Dual-port Caches

(1)

4.11 Increasing the Hit Rate by Adding an L2 Cache

(1)

4.12 Operations to Ensure Cache Coherency

(1)

4.12.1 Write-Through

(1)

4.12.2 Copy-Back

(1)

4.13 External Cache Subsystems

(5)

4.13.1 Types of SRAMs Used for Cache Tags

(4)

4.14 SRAMs Tailored for Cache Data RAMs

(7)

4.14.1 Asynchronous Cache SRAMs

(1)

4.14.2 Synchronous Cache SRAMs

(1)

4.14.3 Burst Mode on Synchronous Cache SRAMs

(4)

4.14.4 Pipelined Burst SSRAMs

(2)

4.15 Use of Parity in Caches

(3)

Bibliography

(1)

5 Evolution of Fast Asynchronous DRAMs

(40)

5.1 Overview

(3)

5.2 Basic DRAM Operation

100

(2)

5.3 Early Speed Improvements

102

(6)

5.3.1 Nibble Mode

103

(2)

5.3.2 Wide I/O

105

(3)

5.4 Special Access Modes

108

(24)

5.4.1 Page Mode

108

(1)

5.4.2 Fast (Enhanced) Page Mode

109

(4)

5.4.3 Static Column Mode

113

(1)

5.4.4 Fast Page with EDO (Hyperpage)

114

(7)

5.4.5 Hyperpage Mode with Output Enable Control

121

(1)

5.4.6 Hyperpage Mode with Write Enable Control

122

(2)

5.4.7 Burst Mode with EDO

124

(4)

5.4.8 Pipeline Burst EDO

128

(4)

5.5 Technology Speed Trends

132

(1)

5.5.1 High Density 64M and 256M EDO DRAMS

133

(1)

5.6 Other Factors in DRAM Speed

133

(3)

5.6.1 Access Time vs. Power Supply Voltage

133

(2)

5.6.2 Low Temperature Operation for Speed

135

(1)

5.6.3 Address Demultiplexed DRAMs

135

(1)

5.6.4 BiCMOS DRAMs for Speed

136

(1)

5.7 Early Experiments in High Speed

136

(1)

Bibliography

136

(1)

6 New Architectures for Fast DRAMs

137

(88)

6.1 Overview

137

(2)

6.2 Synchronous Interface on DRAMs

139

(2)

6.3 High Speed Modes on Synchronous DRAMs

141

(1)

6.4 Pipelining on Synchronous DRAMs

142

(1)

6.5 Prefetch Architectures in Synchronous DRAMs

143

(1)

6.6 Combinations of Pipelining and Prefetch

144

(1)

6.7 Multiple Internal Banks

145

(3)

6.8 Overview of Types of Synchronous DRAMs

148

(1)

6.9 The Early 16M JEDEC SDRAMs

148

(3)

6.9.1 Features

148

(1)

6.9.2 New Pin Function Descriptions

149

(2)

6.10 Architecture of JEDEC SDRAMs

151

(1)

6.10.1 Synchronous and Registered Inputs and Outputs

151

(1)

6.10.2 Multiple Internal Banks

152

(1)

6.10.3 Output Structure

152

(1)

6.11 Operational Features

152

(3)

6.11.1 Mode Register

152

(2)

6.11.2 Burst Mode Access

154

(1)

6.11.3 CAS Latency

154

(1)

6.11.4 Chip Select Latency

155

(1)

6.12 Operational Functions of the SDRAM Truth Table

155

(6)

6.12.1 SDRAM Truth Table

155

(1)

6.12.2 Auto-Precharge

156

(1)

6.12.3 External Precharge Timing

157

(1)

6.12.4 Write Latency

158

(2)

6.12.5 DQM Latency for Reads

160

(1)

6.12.6 DQM Latency for Writes

160

(1)

6.12.7 The 2-N Rule

160

(1)

6.13 Refresh and Power Down on the JEDEC SDRAM

161

(2)

6.13.1 Auto Refresh Function

162

(1)

6.13.2 Self Refresh

162

(1)

6.14 Power Down and Clock Enable

163

(3)

6.14.1 Clock Enable

163

(1)

6.14.2 Power Down

163

(1)

6.14.3 Clock Suspend

163

(3)

6.15 A State Diagram for the JEDEC SDRAM

166

(1)

6.16 Power On Sequence for the JEDEC SDRAM

166

(2)

6.17 Interface Options for the JEDEC SDRAM

168

(1)

6.18 64M, 128M, and 256M SDRAM I (SDR)

168

(11)

6.18.1 64M SDRAM I

168

(10)

6.18.2 128M and 256M SDRAM I

178

(1)

6.19 SDRAM II--Double Data Rate SDRAM

179

(11)

6.20 Trends in SDRAM Characteristics

190

(1)

6.21 Cache DRAMs

191

(21)

6.21.1 Introduction

191

(2)

6.21.2 The Enhanced DRAM

193

(4)

6.21.3 Enhanced Synchronous DRAM I

197

(4)

6.21.4 Enhanced Synchronous DRAM II (DDR)

201

(1)

6.21.5 The CDRAM

202

(9)

6.21.6 Virtual Channel SDRAM

211

(1)

6.22 Packet Protocol Synchronous DRAMs

212

(11)

6.22.1 Packet Protocol Synchronous DRAMs from Rambus, Inc.

213

(8)

6.22.2 Synchronous Link DRAM (SLDRAM)

221

(2)

Bibliography

223

(2)

7 Graphics DRAMs

225

(50)

7.1 Overview of DRAMs for Graphics Subsystems

225

(1)

7.2 Frame Memories for Television Applications

226

(3)

7.2.1 Simple Serial Field Memory for Temporary Frame Storage

226

(1)

7.2.2 Serial DRAM for High Definition TV Frame Storage

227

(2)

7.3 Single Port Asynchronous DRAMs for Graphics Applications

229

(1)

7.3.1 Wide DRAM for Unified Memory in Low End PC

229

(1)

7.3.2 Wide DRAM for High Speed Printer Graphics

230

(1)

7.4 Graphics Features on Asynchronous Single Port DRAMs

230

(2)

7.4.1 Write-Per-Bit

230

(2)

7.4.2 Persistent Write-Per-Bit

232

(1)

7.5 Synchronous Single Port DRAMs Used in Graphics Systems

232

(5)

7.5.1 4M Synchronous Graphics DRAMs

233

(3)

7.5.2 8M SGRAMs

236

(1)

7.6 Special Graphics Features on SGRAMs

237

(8)

7.6.1 Load Special Mode Register Cycle

239

(1)

7.6.2 Load Mask Register

239

(1)

7.6.3 Load Color Register

239

(2)

7.6.4 Active Graphics Commands

241

(1)

7.6.5 Masked Write-Per-Bit

242

(1)

7.6.6 Block Write

243

(1)

7.6.7 Clock Enable on SGRAM

243

(1)

7.6.8 Current State Truth Table on SGRAM

243

(2)

7.7 16M SGRAMs

245

(1)

7.8 Other Single Port Graphics DRAMs

246

(6)

7.8.1 Synchronous Protocol DRAM from Rambus, Inc.

247

(3)

7.8.2 Multiple Bank DRAM from Mosys

250

(2)

7.9 Overview of Multi-Port Graphics DRAMs (VRAMs)

252

(1)

7.10 An Introduction to VRAMs, the 4M VRAMs

253

(1)

7.11 RAM Operations

254

(3)

7.11.1 Extended Read and Write Mode

255

(1)

7.11.2 Random Port Mask Functions

255

(2)

7.11.3 Flash Write

257

(1)

7.12 Transfer Operations between the RAM and SAM

257

(3)

7.12.1 256 x 16 SAM

257

(2)

7.12.2 512 x 16 SAM

259

(1)

7.13 SAM Operation

260

(1)

7.14 Video DRAM Standards and Market

261

(1)

7.15 8M Video DRAM

262

(2)

7.15.1 Samsung "Window RAM"

262

(2)

7.16 8M and 16M Synchronous VRAMs

264

(1)

7.17 Triple Port VRAM

265

(2)

7.18 VRAMs with Z-buffers

267

(1)

7.18.1 3D-RAM

267

(1)

7.19 DDR SGRAMs

267

(1)

7.20 Dual Port Graphics DRAM

268

(2)

7.21 Integrated Frame Buffers

270

(2)

Bibliography

272

(3)

8 Power Supply, Interface, and Test Issues

275

(22)

8.1 Different Voltages in the System

275

(2)

8.2 Fast Interfaces

277

(14)

8.2.1 Established Interfaces

277

(4)

8.2.2 Newer High Speed Interfaces

281

(9)

8.2.3 Packet Protocol DRAM Interfaces

290

(1)

8.3 Difficulties in Specification of High Speed Components

291

(1)

8.4 Testing High Speed Memories

291

(5)

8.4.1 Testing High Density Memories

291

(1)

8.4.2 Testing Stand-alone RAMs using BIST

292

(1)

8.4.3 Testing with Boundary Scan

292

(1)

8.4.4 Testing High Speed RAMs

293

(2)

8.4.5 Power and Heat Management

295

(1)

Bibliography

296

(1)

9 Fast Packaging Techniques

297

(32)

9.1 Fast Memory Component Packaging

297

(1)

9.2 Packages for Fast DRAMs

297

(4)

9.2.1 Trends to Smaller Sizes in Commodity DRAM Packages

297

(1)

9.2.2 Reverse Pinout Packages for Double Sided Modules

298

(1)

9.2.3 Vertical DRAM Packages

298

(1)

9.2.4 Speciality DRAM Packages

299

(2)

9.3 DRAM SIMM and DIMM Modules

301

(15)

9.3.1 8/9 Bit SIMM Modules

301

(2)

9.3.2 "x32" SIMM Modules (72-Pin SIMM)

303

(2)

9.3.3 Small Outline 72-Pin DIMMs

305

(1)

9.3.4 168-Pin 64/72-Bit (8-Byte) DRAM DIMM Module

306

(6)

9.3.5 72-Bit (8-Byte) 200-Pin Synchronous DRAM DIMM Module

312

(4)

9.4 Fast SRAM Packages

316

(6)

9.4.1 Packages for Fast Synchronous SRAMs

317

(3)

9.4.2 Speed Considerations in SRAM Package Selection

320

(1)

9.4.3 Trends in Systems Using Miniature Packaging

321

(1)

9.5 SRAM Modules

322

(4)

9.5.1 Multi-Package SRAM Modules

322

(1)

9.5.2 SRAM Multichip Packages and Multichip Modules

322

(3)

9.5.3 SRAM Multichip Modules

325

(1)

9.6 Package Considerations in Replacing or Upgrading a Cache SRAM

326

(2)

9.6.1 General Considerations

326

(1)

9.6.2 First Generation Upgrades

327

(1)

9.6.3 Second Generation Upgrades

327

(1)

9.6.4 Next Generation System Redesigns

328

(1)

Bibliography

328

(1)

Index

329

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High Performance Memories New Architecture DRAMs and SRAMs - Evolution and Function

Summary

Author Biography

Table of Contents

Supplemental Materials