Modern VLSI Design IP-Based Design

The Number 1 VLSI Design Guide-Now Fully Updated for IP-Based Design and the Newest Technologies Modern VLSI Design, Fourth Edition,offers authoritative, up-to-the-minute guidance for the entire VLSI design process-from architecture and logic design through layout and packaging. Wayne Wolf has systematically updated his award-winning book for todayrs"s newest technologies and highest-value design techniques. Wolf introduces powerful new IP-based design techniques at all three levels: gates, subsystems, and architecture. He presents deeper coverage of logic design fundamentals, clocking and timing, and much more. No other VLSI guide presents as much up-to-date information for maximizing performance, minimizing power utilization, and achieving rapid design turnarounds. Coverage includes All-new material on IP-based design Extensive new coverage of networks-on-chips New coverage of using FPGA fabrics to improve design flexibility New material on image sensors, busses, Rentrs"s Rule, pipelining, and more Updated VLSI technology parameters reflecting the latest advances Revised descriptions of HDLs and other VLSI design tools Advanced techniques for overcoming bottlenecks and reducing crosstalk Low-power design techniques for enhancing reliability and extending battery life Testing solutions for every level of abstraction, from gates to architecture Revamped end-of-chapter problems that fully reflect todayrs"s VLSI design challenges Wolf introduces a top-down, systematic design methodology that begins with high-level models, extends from circuits to architecture, and facilitates effective testing. Along the way, he brings together all the skills VLSI design professionals will need to create tomorrowrs"s state-of-the-art devices.

Wayne Wolf is Rhesa “Ray” S. Farmer Jr. Distinguished Chair in Embedded Computing Systems and Georgia Research Alliance Eminent Scholar at the Georgia Institute of Technology. Before joining Georgia Tech, he was with Princeton University from 1989 to 2007 and AT&T Bell Laboratories from 1984 to 1989. He received the B.S., M.S., and Ph.D. degrees in electrical engineering from Stanford University in 1980, 1981, and 1984, respectively. His research interests include VLSI systems, embedded computing, cyber-physical systems, and embedded computer vision. He has chaired several conferences, including CODES, EMSOFT, CASES, and ICCD. He was founding editor-in-chief of ACM Transactions on Embedded Computing Systems and founding co-editor-in-chief of Design Automation for Embedded Systems. He is a Fellow of the ACM and IEEE. He received the ASEE/CSE and HP Frederick E. Terman Award in 2003 and the IEEE Circuits and Systems Education Award in 2006.

Preface to the Fourth Edition	p. xv
Preface to the Third Edition	p. xvii
Preface to the Second Edition	p. xviii
Preface	p. xix
About the Author	p. xxii
Digital Systems and VLSI	p. 1
Why Design Integrated Circuits?	p. 3
Integrated Circuit Manufacturing	p. 5
CMOS Technology	p. 18
Integrated Circuit Design Techniques	p. 21
IP-Based Design	p. 33
A Look into the Future	p. 40
Summary	p. 41
References	p. 42
Problems	p. 42
Fabrication and Devices	p. 43
Introduction	p. 45
Fabrication Processes	p. 45
Transistors	p. 52
Wires and Vias	p. 73
Fabrication Theory and Practice	p. 84
Reliability	p. 98
Layout Design and Tools	p. 103
References	p. 119
Problems	p. 120
Logic Gates	p. 123
Introduction	p. 125
Combinational Logic Functions	p. 125
Static Complementary Gates	p. 128
Switch Logic	p. 157
Alternative Gate Circuits	p. 159
Low-Power Gates	p. 169
Delay through Resistive Interconnect	p. 175
Delay through Inductive Interconnect	p. 187
Design-for-Yield	p. 193
Gates as IP	p. 195
References	p. 198
Problems	p. 199
Combinational Logic Networks	p. 205
Introduction	p. 207
Standard Cell-Based Layout	p. 207
Combinational Network Delay	p. 219
Logic and Interconnect Design	p. 235
Power Optimization	p. 246
Switch Logic Networks	p. 251
Combinational Logic Testing	p. 255
References	p. 262
Problems	p. 262
Sequential Machines	p. 267
Introduction	p. 269
Latches and Flip-Flops	p. 269
Sequential Systems and Clocking Disciplines	p. 281
Performance Analysis	p. 292
Clock Generation	p. 310
Sequential System Design	p. 312
Power Optimization	p. 329
Design Validation	p. 330
Sequential Testing	p. 332
References	p. 340
Problems	p. 340
Subsystem Design	p. 345
Introduction	p. 347
Combinational Shifters	p. 349
Adders	p. 352
ALUs	p. 360
Multipliers	p. 360
High-Density Memory	p. 369
Image Sensors	p. 382
Field-Programmable Gate Arrays	p. 385
Programmable Logic Arrays	p. 387
Buses and Networks-on-Chis	p. 391
Data Paths	p. 415
Subsystems as IP	p. 417
References	p. 422
Problems	p. 422
Floorplanning	p. 425
Introduction	p. 427
Floorplanning Methods	p. 427
Global Interconnect	p. 439
Floorplan Design	p. 450
Off-Chip Connections	p. 452
References	p. 461
Problems	p. 462
Architecture Design	p. 471
Introduction	p. 473
Hardware Description Languages	p. 473
Register-Transfer Design	p. 495
Pipelining	p. 509
High-Level Synthesis	p. 518
Architectures for Low Power	p. 539
GALS Systems	p. 544
Architecture Testing	p. 545
IP Components	p. 550
Design Methodologies	p. 551
Multiprocessor System-on-Chip Design	p. 559
References	p. 565
Problems	p. 565
A Chip Designer's Lexicon	p. 571
Hardware Description Languages	p. 589
Introduction	p. 589
Verilog	p. 589
VHDL	p. 594
References	p. 599
Index	p. 613
Table of Contents provided by Publisher. All Rights Reserved.

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Modern VLSI Design IP-Based Design

Summary

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Table of Contents

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