Low-Power CMOS Design

, by Chandrakasan, Anantha; Brodersen, Robert W.

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ISBN: 9780780334298 | 0780334299
Cover: Hardcover
Copyright: 2/11/1998

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This collection of important papers provides a comprehensive overview of low-power system design, from component technologies and circuits to architecture, system design, and CAD techniques. LOW POWER CMOS DESIGN summarizes the key low-power contributions through papers written by experts in this evolving field.

Preface

Part I Overview

(58)

1.1 Low Power Microelectronics: Retrospect and Prospect

(17)

J. Meindl (Proceedings of the IEEE, April 1995).

1.2 Micropower IC

(16)

E. Vittoz (Proceedings of the IEEE European Solid State Circuits Conference, Grenoble, September 1980).

1.3 Low-Power CMOS Digital Design

(11)

A.P. Chandrakasan

S. Sheng

R.W. Brodersen (IEEE Journal of Solid State Circuits, April 1992).

1.4 CMOS Scaling for High Performance and Low-Power-The Next Ten Years

(12)

B. Davari

R. Dennard

G. Shahidi (Proceedings of the IEEE, April 1995).

Part II Low Voltage Technologies and Circuits

(68)

2.1 Low-Voltage Technologies and Circuits

(5)

T. Kuroda

T. Sakurai (INVITED PAPER).

SECTION 2.1 Threshold Voltage Scaling and Control

(20)

2.2 Ion-Implanted Complementary MOS Transistors in Low-Voltage Circuits

(8)

R.M. Swanson

J.D. Meindl (IEEE Journal of Solid-State Circuits, April 1972).

2.3 Trading Speed for Low Power by Choice of Supply and Threshold Voltages

(8)

D. Liu

C. Svensson (IEEE Journal of Solid-State Circuits, January 1993).

2.4 Limitation of CMOS Supply-Voltage Scaling by MOSFET Threshold-Voltage Variation

(4)

S. Sun

P. Tsui (IEEE Custom Integrated Circuits Conference, May 1994).

SECTION 2.2 Multiple Threshold CMOS (MTCMOS)

(9)

2.5 1-V Power Supply High-Speed Digital Circuit Technology with Multithreshold Voltage CMOS

(7)

S. Mutoh

T. Douskei

Y. Matsuya

T. Aoki

S. Shigematsu

J. Yamada (IEEE Journal of Solid-State Circuits, August 1995).

2.6 A 1-V Multi-Threshold Voltage CMOS DSP with an Efficient Power Management Technique for Mobile Phone Application

(2)

S. Mutoh

S. Shigematsu

Y. Matsuya

H. Fukuda

J. Yamada (IEEE International Solid-State Circuits Conference, February 1996).

SECTION 2.3 Substrate Bias Controlled Variable Threshold CMOS

(10)

2.7 50% Active-Power Saving Without Speed Degradation Using Standby Power Reduction (SPR) Circuit

(2)

K. Seta

H. Hara

T. Kuroda

M. Kakumu

T. Sakurai (IEEE International Solid-State Circuits Conference, February 1995).

2.8 A 0.9V, 150MHz 10mW 4mm(2), 2-D Discrete Cosine Transform Core Processor with Variable Threshold-Voltage (VT) Scheme

(8)

T. Kuroda

T. Fujita

S. Mita

T. Nagamatsu

S. Yoshioka

K. Suzuki

F. Sano

M. Norishima

M. Murota

M. Kako

M. Kinugawa

M. Kakumu

T. Sakurai (IEEE Journal of Solid-State Circuits, November 1996).

SECTION 2.4 Silicon-on-Insulator Based Technologies

105

(22)

2.9 SOI CMOS for Low Power Systems

105

(6)

D. Antoniadis (INVITED PAPER).

2.10 Back Gated CMOS on SOIAS for Dynamic Threshold Voltage Control

111

(4)

I. Yang

C. Vieri

A.P. Chandrakasan

D. Antoniadis (IEEE International Electron Devices Meeting (IEDM), December 1995).

2.11 Design of Low Power CMOS/SOI Devices and Circuits for Memory and Signal Processing Applications

115

(6)

L. Thon

G. Shahidi (INVITED PAPER).

2.12 A Dynamic Threshold Voltage MOSFET (DTMOS) for Very Low Voltage Operation

121

(3)

F. Assaderaghi

S. Parke

D. Sinitsky

J. Bokor

P.K. Ko

C. Hu (IEEE Electron Device Letters, December 1994).

2.13 A 0.5V SIMOX-MTCMOS Circuit with 200ps Logic Gate

124

(3)

T. Douseki

S. Shigematsu

Y. Tanabe

M. Harada

H. Inokawa

T. Tsuchiya (IEEE International Solid-State Circuits Conference, February 1996).

Part III Efficient DC-DC Conversion and Adaptive Power Supply Systems

127

(62)

SECTION 3.1 Efficient Low Voltage DC-DC Converter Design

129

(14)

3.1 A Low-Voltage CMOS DC-DC Converter for a Portable Battery-Operated System

129

(8)

A. Stratakos

S. Sanders

R. Brodersen (IEEE Power Electronics Specialists Conference, 1994).

3.2 Ultra Low-Power Control Circuits for PWM Converters

137

(6)

A. Dancy

A. Chandrakasan (CONTRIBUTED PAPER).

SECTION 3.2 Adaptive Power Supply Systems

143

(46)

3.3 A Voltage Reduction Technique for Battery Operated Systems

143

(5)

V. von Kaenel

P. Macken

M. Degrauwe (IEEE Journal of Solid-State Circuits, October 1990).

3.4 Automatic Adjustment of Threshold and Supply Voltage for Minimum Power Consumption in CMOS Digital Circuits

148

(2)

V. von Kaenel

M. Pardoen

E. Dijkstra

E. Vittoz (IEEE Symposium on Low-Power Electronics, October 1994).

3.5 Low-Power Operation Using Self-Timed Circuits and Adaptive Scaling of the Supply Voltage

150

(7)

L. Nielsen

C. Niessen

J. Sparso

K. van Berkel (IEEE Transactions on VLSI Systems, December 1994).

3.6 A Low-Power Switching Power Supply for Self-Clocked Systems

157

(9)

G. Wei

M. Horowitz (INVITED PAPER).

3.7 Variable-Voltage Digital-Signal Processing

166

(11)

V. Gutnik

A. Chandrakasan (CONTRIBUTED PAPER).

3.8 Scheduling for Reduced CPU Energy

177

(12)

M. Weiser

B. Welch

A. Demers

S. Shenker (First Symposium on Operating Systems Design and Implementation (OSDI), Usenix Association, 1994).

Part IV Circuit and Logic Styles

189

(84)

SECTION 4.1 Conventional Circuit and Logic Styles

191

(48)

4.1 Silicon-Gate CMOS Frequency Divider for the Electronic Wrist Watch

191

(5)

E. Vittoz

B. Gerber

F. Leuenberger (IEEE Journal of Solid-State Circuits, April 1972).

4.2 CODYMOS Frequency Dividers Achieve Low Power Consumption and High Frequency

196

(2)

H. Oguey

E. Vittoz (Electronics Letters, July 1973).

4.3 Short-Circuit Dissipation of Static CMOS Circuitry and Its Impact on the Design of Buffer Circuits

198

(6)

H.J.M. Veendrick (IEEE Journal of Solid-State Circuits, August 1984).

4.4 A 3.8ns CMOS 16 X 16 Multiplier Using Complementary Pass Transistor Logic

204

(4)

K. Yano

T. Yamanaka

T. Nishida

M. Saitoh

K. Shimohigashi

A. Shimizu. (IEEE Custom Integrated Circuits Conference, 1989).

4.5 A High-Speed, Low-Power, Swing Restored Pass-Transistor Logic Based Multiply and Accumulate Circuit for Multimedia Applications

208

(4)

A. Parameswar

H. Hara

T. Sakurai (Proceedings of Custom Integrated Circuits Conference, May 1994).

4.6 Static Power Driven Voltage Scaling and Delay Driven Buffer Sizing in Mixed Swing QuadRail for Sub-IV I/O Swings

212

(6)

R. Krishnamurthy

I. Lys

L.R. Carley (International Symposium on Low-Power Electronics and Design, August 1996).

4.7 The Power Consumption of CMOS Adders and Multipliers

218

(7)

T. Callaway

E. Swartzlander, Jr. (INVITED PAPER).

4.8 Delay Balanced Multipliers for Low Power/Low Voltage DSP Core

225

(2)

T. Sakuta

W. Lee

P.T. Balsara (IEEE Symposium on Low-Power Electronics: Digest of Technical Papers, October 1995).

4.9 Asynchronous Does Not Imply Low Power, But

227

(6)

K. Van Berkel

H. van Gageldonk

J. Kessels

C. Niessen

A. Peeters

M. Roncken

R. van de Wiel (INVITED PAPER).

4.10 Latches and Flip-Flops for Low-Power Systems

233

(6)

C. Svensson

J. Yuan (INVITED PAPER).

SECTION 4.2 Adiabatic Logic Circuits

239

(34)

4.11 Zig-Zag Path to Understanding

239

(6)

R. Landauer (IEEE PhysComp '94).

4.12 A Low-Power Multiphase Circuit Technique

245

(8)

B. Watkins (IEEE Journal of Solid-State Circuits, December 1967).

4.13 Asymptotically Zero Energy Split-Level Charge Recovery Logic

253

(6)

S. Younis

T. Knight (International Workshop on Low Power Design, 1994).

4.14 Low Power Digital Systems Based on Adiabatic Switching Principles

259

(9)

W.C. Athas

L. Sevensson

J.G. Koller

N. Tzartzanis

E.Y. Chou (IEEE Trans. on VLSI Systems, December 1994).

4.15 Adiabatic Dynamic Logic

268

(5)

A. Dickinson

J. Denker (IEEE Journal of Solid-State Circuits, March 1995).

Part V Driving Interconnect

273

(38)

5.1 Sub-1-V Swing Internal Bus Architecture for Future Low-Power ULSIs

275

(6)

Y. Nakagome

K. Itoh

M. Isoda

K. Takeuchi

M. Aoki (IEEE Journal of Solid-State Circuits, April 1993).

5.2 Data-Dependent Logic Swing Internal Bus Architecture for Ultra Low-Power LSIs

281

(6)

M. Hiraki

H. Kojima

H. Misawa

T. Akazawa

Y. Hatano (IEEE Journal of Solid-State Circuits, April 1995).

5.3 An Asymptotically Zero Power Charge-Recycling Bus Architecture for Battery-Operated Ultra-High Data Rate ULSIs

287

(9)

H. Yamauchi

H. Akamatsu

T. Fujita (IEEE Journal of Solid-State Circuits, April 1995).

5.4 Bus-Invert Coding for Low Power I/O

296

(10)

M. Stan

W. Burleson (IEEE Trans. on VLSI Systems, March 1995).

5.5 A Sub-CV(2) Pad Driver with 10 ns Transition Time

306

(5)

L.J. Svensson

W.C. Athas

R.S-C. Wen (IEEE International Symposium on Low-Power Electronics and Design, August 1996).

Part VI Memory Circuits

311

(56)

6.1 Reviews and Prospects of Low-Power Memory Circuits

313

(5)

K. Itoh (INVITED PAPER).

SECTION 6.1 DRAM

318

(34)

6.2 Trends in Low-Power RAM Circuit Technologies

318

(20)

K. Itoh

K. Sasaki

Y. Nakagome (Proceedings of the IEEE, April 1995).

6.3 Standby/Active Mode Logic for Sub-1V Operating ULSI Memory

338

(6)

D. Takashima

S. Watanabe

H. Nakano

Y. Oowaki

K. Ohuchi

H. Tango (IEEE Journal of Solid-State Circuits, April 1994).

6.4 A Charge Recycle Refresh for Gb-scale DRAM's in File Application

344

(8)

T. Kawahara

Y. Kawajiri

M. Horiguchi

T. Akiba

G. Kitsukawa

T. Kure

M. Aoki (IEEE Journal of Solid-State Circuits, June 1994).

SECTION 6.2 SRAM

352

(15)

6.5 A 1-V 1-Mb SRAM for Portable Equipment

352

(6)

H. Morimura

N. Shibata (International Symposium on Low-Power Electronics and Design, August 1996).

6.6 A Single Bitline Cross-Point Cell Activation (SCPA) Architecture for Ultra-Low-Power SRAMs

358

(2)

M. Ukita

S. Murakami

T. Yamagata

H. Kuriyama

Y. Nishimura

K. Anami (IEEE International Solid-State Circuits Conference, February 1994).

6.7 Techniques to Reduce Power in Fast Wide Memories

360

(2)

B. Amrutur

M. Horowitz (Proceedings of the IEEE Symposium on Low Power Electronics, 1994).

6.8 A 2-ns, 5-mW, Synchronous-Powered Static-Circuit Fully Associative TLB

362

(2)

H. Higuchi

S. Tachibana

M. Minami

T. Nagano (IEEE Symposium on VLSI Circuits, June 1995).

6.9 Driving Source-Line (DSL) Cell Architecture for Sub-1-V High Speed Low Power Applications

364

(3)

H. Mizuno

T. Nagano (IEEE Symposium of VLSI Circuits, June 1995).

Part VII Portable Terminal Electronics

367

(90)

SECTION 7.1 General Purpose Processor Design

369

(35)

7.1 Energy Dissipation in General Purpose Microprocessors

369

(7)

R. Gonzalez

M. Horowitz (IEEE Journal of Solid-State Circuits, September 1996).

7.2 Energy Efficient CMOS Microprocessor Design

376

(10)

T. Burd

R. Brodersen (Proceedings of the 28th Annual HICSS Conference, January 1995).

7.3 A 160MHz 32b 0.5W CMOS RISC Microprocessor

386

(10)

J. Montanaro

R. Witek

K. Anne

A. Black

E. Cooper

D. Dobberpuhl

P. Donahue

J. Eno

G. Hoeppner

D. Kruckemyer

T. Lee

P. Lin

L. Madden

D. Murray

M. Pearce

S. Santhanam

K. Snyder

R. Stephany

S. Thierauf (IEEE Journal of Solid-State Circuits, November 1996).

7.4 A 320Mhz, 1.5mW @ 1.35V CMOS PLL for Microprocessor Clock Generation

396

(8)

V. Von Kaenel

D. Aebischer

C. Piguet

E. Dijkstra (IEEE Journal of Solid-State Circuits, November 1996).

SECTION 7.2 Dedicated and Programmable Digital Signal Processors

404

(53)

7.5 A Low-Power Chipset for a Portable Multimedia I/O Terminal

404

(14)

A.P. Chandrakasan

A. Burstein

R.W. Brodersen (IEEE Journal of Solid-State Circuits, December 1994).

7.6 A Portable Real-Time Video Decoder for Wireless Communication

418

(15)

T. Meng

B. Gordon

E. Tsern (INVITED PAPER).

7.7 Low Power Design of Memory Intensive Functions

433

(2)

D. Lidsky

J. Rabaey (IEEE Symposium on Low-Power Electronics, 1994).

7.8 A 16b Low-Power Digital Signal Processor

435

(2)

K. Ueda

T. Sugimura

M. Okamoto

S. Marui

T. Ishikawa

M. Sakakihara (IEEE International Solid-State Circuits Conference, February 1993).

7.9 A 1.8V 36mW DSP for the Half-Rate Speech CODEC

437

(4)

T. Shiraishi

K. Kawamoto

K. Ishikawa

H. Sato

F. Asai

E. Teraoka

T. Kengaku

H. Takata

T. Tokuda

K. Nishida

K. Saitoh (Proceedings of the IEEE Custom Integrated Circuits Conference, May 1996).

7.10 Design of a 1-V Programmable DSP for Wireless Communication

441

(9)

P. Landman

W. Lee, B. Barton

S. Abiko

H. Takahashi

H. Mizuno. S. Muramatsu

K. Tashiro

M. Fusumada

L. Pham

F. Boutaud

E. Ego

G. Gallo

H. Tran

C. Lemonds

A. Shih

M. Nandakumar

B. Eklund

I-C. Chen (INVITED PAPER).

7.11 Stage-Skip Pipeline: A Low Power Processor Architecture Using a Decoded Instruction Buffer

450

(7)

M. Hiraki

R. Bajwa

H. Kojima

D. Gorny

K. Nitta

A. Shridhar

K. Sasaki

K. Seki (International Symposium on Low Power Electronics and Design, August 1996).

Part VIII Computer Aided Design Tools

457

(162)

SECTION 8.1 Power Analysis Techniques

459

(83)

8.1 Transition Density: A New Measure of Activity in Digital Circuits

459

(14)

F. Najm (IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems, February 1993).

8.2 Estimation of Average Switching Activity in Combinational and Sequential Circuits

473

(7)

A. Ghosh

S. Devadas

K. Keutzer

J. White (IEEE/ACM Design Automation Conference, June 1992).

8.3 Power Estimation for Sequential Logic Circuits

480

(12)

C. Tsui

J. Monteiro

M. Pedram

S. Devadas

A. Despain

B. Lin (IEEE Trans. on VLSI Systems, September 1995).

8.4 A Monte Carlo Approach for Power Estimation

492

(9)

R. Burch

F.N. Najm

P. Yang

T. Trick (IEEE Transactions on VLSI Systems, March 1993).

8.5 Stratified Random Sampling for Power Estimation

501

(7)

C.-S. Ding

C.-T. Hsieh

Q. Wu

M. Pedram (IEEE/ACM International Conference on Computer-Aided Design, November 1996).

8.6 A Survey of High-Level Power Estimation Techniques

508

(8)

P. Landman (INVITED PAPER).

8.7 Activity-Sensitive Architectural Power Analysis

516

(17)

P. Landman

J. Rabaey (IEEE Transactions on CAD, June 1996).

8.8 Power Analysis of Embedded Software: A First Step Towards Software Power Minimization

533

(9)

V. Tiwari

S. Malik

A. Wolfe (IEEE Trans. on VLSI Systems, December 1994).

SECTION 8.2 Power Optimization Techniques

542

(77)

8.9 Technology Mapping for Low Power

542

(6)

V. Tiwari

P. Ashar

S. Malik (Proceedings of the IEEE/ACM 30th Design Automation Conference, June 1993).

8.10 POSE: Power Optimization and Synthesis Environment

548

(6)

S. Iman

M. Pedram (IEEE/ACM 33rd Design Automation Conference, June 1996).

8.11 Transformation and Synthesis of FSMs for Low-Power Gated-Clock Implementation

554

(6)

L. Benini

G. De Micheli (International Symposium of Low Power Design, April 1995).

8.12 Precomputation-Based Sequential Logic Optimization for Low Power

560

(8)

M. Alidina

J. Monteiro

S. Devadas

A. Ghosh

M. Papaefthymiou (Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, November 1994).

8.13 Glitch Analysis and Reduction in Register Transfer Level Power Optimization

568

(6)

A. Raghunathan

S. Dey

N. Jha (IEEE/ACM 33rd Design Automation Conference, June 1996).

8.14 Exploiting Locality for Low-Power Design

574

(4)

R. Mehra

L. Guerra

J. Rabaey (Proceedings of the IEEE Custom Integrated Circuit Conference, May 1996).

8.15 HYPER-LP: A System for Power Minimization Using Architectural Transformations

578

(4)

A.P. Chandrakasan

M. Potkonjak

J. Rabaey

R.W. Brodersen (IEEE/ACM International Conference on Computer-Aided Design, November 1992).

8.16 Variable Voltage Scheduling

582

(27)

S. Raje

M. Sarrafzadeh (International Symposium on Low Power Design, April 1995).

8.17 System-Level Transformations for Low Power Data Transfer and Storage

609

(10)

F. Catthoor

S. Wuytack

E. de Greef

F. Franssen

L. Nachtergaele

H. Deman (INVITED PAPER).

Author Index

619

(4)

Index

623

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Low-Power CMOS Design

Summary

Author Biography

Table of Contents

Supplemental Materials