Digital Integrated Circuits

, by Rabaey, Jan M.; Chandrakasan, Anantha; Nikolic, Borivoje

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ISBN: 9780130909961 | 0130909963
Cover: Paperback
Copyright: 12/24/2002

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Progressive in content and form, this practical book successfully bridges the gap between the circuit perspective and system perspective of digital integrated circuit design.Digital Integrated Circuitsmaintains a consistent, logical flow of subject matter throughout.Addresses today's most significant and compelling industry topics, including: the impact of interconnect, design for low power, issues in timing and clocking, design methodologies, and the tremendous effect of design automation on the digital design perspective.For readers interested in digital circuit design.

Preface

vii

Part 1 The Fabrics

(66)

Introduction

(32)

A Historical Perspective

(2)

Issues in Digital Integrated Circuit Design

(9)

Quality Metrics of a Digital Design

(16)

Cost of an Integrated Circuit

(2)

Functionality and Robustness

(9)

Performance

(3)

Power and Energy Consumption

(1)

Summary

(1)

To Probe Further

(4)

Reference Books

(1)

References

(2)

The Manufacturing Process

(32)

Introduction

(1)

Manufacturing CMOS Integrated Circuits

(11)

The Silicon Wafer

(1)

Photolithography

(4)

Some Recurring Process Steps

(1)

Simplified CMOS Process Flow

(5)

Design Rules---The Contract between Designer and Process Engineer

(4)

Packaging Integrated Circuits

(10)

Package Materials

(1)

Interconnect Levels

(6)

Thermal Considerations in Packaging

(2)

Perspective---Trends in Process Technology

(3)

Short-Term Developments

(2)

In the Longer Term

(1)

Summary

(1)

To Probe Further

(3)

References

(3)

Design Methodology Insert A IC LAYOUT

(64)

To Probe Further

(2)

References

(2)

The Devices

(58)

Introduction

(1)

The Diode

(13)

A First Glance at the Diode---The Depletion Region

(2)

Static Behavior

(3)

Dynamic, or Transient, Behavior

(4)

The Actual Diode---Secondary Effects

(1)

The SPICE Diode Model

(2)

The MOS(FET) Transistor

(33)

A First Glance at the Device

(1)

The MOS Transistor under Static Conditions

(26)

The Actual MOS Transistor---Some Secondary Effects

114

(3)

SPICE Models for the MOS Transistor

117

(3)

A Word on Process Variations

120

(2)

Perspective---Technology Scaling

122

(6)

Summary

128

(1)

To Probe Further

129

(2)

References

130

(1)

Design Methodology Insert B Circuit Simulation

131

(46)

References

134

(1)

The Wire

135

(42)

Introduction

136

(1)

A First Glance

136

(2)

Interconnect Parameters---Capacitance, Resistance, and Inductance

138

(12)

Capacitance

138

(6)

Resistance

144

(4)

Inductance

148

(2)

Electrical Wire Models

150

(20)

The Ideal Wire

151

(1)

The Lumped Model

151

(1)

The Lumped RC Model

152

(4)

The Distributed rc Line

156

(3)

The Transmission Line

159

(11)

SPICE Wire Models

170

(4)

Distributed rc Lines in SPICE

170

(1)

Transmission Line Models in SPICE

170

(1)

Perspective: A Look into the Future

171

(3)

Summary

174

(1)

To Probe Further

174

(3)

References

174

(3)

Part 2 A Circuit Perspective

177

(132)

The CMOS Inverter

179

(56)

Introduction

180

(1)

The Static CMOS Inverter---An Intuitive Perspective

180

(4)

Evaluating the Robustness of the CMOS Inverter: The Static Behavior

184

(9)

Switching Threshold

185

(3)

Noise Margins

188

(3)

Robustness Revisited

191

(2)

Performance of CMOS Inverter: The Dynamic Behavior

193

(20)

Computing the Capacitances

194

(5)

Propagation Delay: First-Order Analysis

199

(4)

Propagation Delay from a Design Perspective

203

(10)

Power, Energy, and Energy Delay

213

(16)

Dynamic Power Consumption

214

(9)

Static Consumption

223

(2)

Putting It All Together

225

(2)

Analyzing Power Consumption Using SPICE

227

(2)

Perspective: Technology Scaling and its Impact on the Inverter Metrics

229

(3)

Summary

232

(1)

To Probe Further

233

(2)

References

233

(2)

Designing Combinational Logic Gates in CMOS

235

(74)

Introduction

236

(1)

Static CMOS Design

236

(48)

Complementary CMOS

237

(26)

Ratioed Logic

263

(6)

Pass-Transistor Logic

269

(15)

Dynamic CMOS Design

284

(19)

Dynamic Logic: Basic Principles

284

(3)

Speed and Power Dissipation of Dynamic Logic

287

(3)

Signal Integrity Issues in Dynamic Design

290

(5)

Cascading Dynamic Gates

295

(8)

Perspectives

303

(3)

How to Choose a Logic Style?

303

(1)

Designing Logic for Reduced Supply Voltages

303

(3)

Summary

306

(1)

To Probe Further

307

(2)

References

308

(1)

Design Methodology Insert C How to Simulate Complex Logic Circuits

309

(10)

Representing Digital Data as a Continuous Entity

310

(1)

Representing Data as a Discrete Entity

310

(5)

Using Higher-Level Data Models

315

(4)

References

317

(2)

Design Methodology Insert D Layout Techniques for Complex Gates

319

(56)

Designing Sequential Logic Circuits

325

(50)

Introduction

326

(4)

Timing Metrics for Sequential Circuits

327

(1)

Classification of Memory Elements

328

(2)

Static Latches and Registers

330

(14)

The Bistability Principle

330

(2)

Multiplexer-Based Latches

332

(1)

Master-Slave Edge-Triggered Register

333

(6)

Low-Voltage Static Latches

339

(2)

Static SR Flip-Flops---Writing Data by Pure Force

341

(3)

Dynamic Latches and Registers

344

(10)

Dynamic Transmission-Gate Edge-triggered Registers

344

(2)

C2MOS---A Clock-Skew Insensitive Approach

346

(4)

True Single-Phase Clocked Register (TSPCR)

350

(4)

Alternative Register Styles*

354

(4)

Pulse Registers

354

(2)

Sense-Amplifier-Based Registers

356

(2)

Pipelining: An Approach to Optimize Sequential Circuits

358

(6)

Latch- versus Register-Based Pipelines

360

(1)

NORA-CMOS---A Logic Style for Pipelined Structures

361

(3)

Nonbistable Sequential Circuits

364

(6)

The Schmitt Trigger

364

(3)

Monostable Sequential Circuits

367

(1)

Astable Circuits

368

(2)

Perspective: Choosing a Clocking Strategy

370

(1)

Summary

371

(1)

To Probe Further

372

(3)

References

372

(3)

Part 3 A System Perspective

375

(52)

Implementation Strategies for Digital ICS

377

(50)

Introduction

378

(4)

From Custom to Semicustom and Structured-Array Design Approaches

382

(1)

Custom Circuit Design

383

(1)

Cell-Based Design Methodology

384

(15)

Standard Cell

385

(5)

Compiled Cells

390

(2)

Macrocells, Megacells and Intellectual Property

392

(4)

Semicustom Design Flow

396

(3)

Array-Based Implementation Approaches

399

(21)

Prediffused (or Mask-Programmable) Arrays

399

(5)

Prewired Arrays

404

(16)

Perspective---The Implementation Platform of the Future

420

(3)

Summary

423

(1)

To Probe Further

423

(4)

References

424

(3)

Design Methodology Insert E Characterizing Logic and Sequential Cells

427

(8)

References

434

(1)

Design Methodology Insert F Design Synthesis

435

(118)

References

443

(2)

Coping with Interconnect

445

(46)

Introduction

446

(1)

Capacitive Parasitics

446

(14)

Capacitance and Reliability---Cross Talk

446

(3)

Capacitance and Performance in CMOS

449

(11)

Resistive Parasitics

460

(9)

Resistance and Reliability---Ohmic Voltage Drop

460

(2)

Electromigration

462

(2)

Resistance and Performance---RC Delay

464

(5)

Inductive Parasitics*

469

(11)

Inductance and Reliability---Voltage Drop

469

(6)

Inductance and Performance---Transmission-line Effects

475

(5)

Advanced Interconnect Techniques

480

(7)

Reduced-Swing Circuits

480

(6)

Current-Mode Transmission Techniques

486

(1)

Perspective: Networks-on-a-Chip

487

(1)

Summary

488

(1)

To Probe Further

489

(2)

References

489

(2)

Timing Issues in Digital Circuits

491

(62)

Introduction

492

(1)

Timing Classification of Digital Systems

492

(3)

Synchronous Interconnect

492

(1)

Mesochronous interconnect

493

(1)

Plesiochronous Interconnect

493

(1)

Asynchronous Interconnect

494

(1)

Synchronous Design---An In-depth Perspective

495

(24)

Synchronous Timing Basics

495

(7)

Sources of Skew and Jitter

502

(6)

Clock-Distribution Techniques

508

(8)

Latch-Based Clocking*

516

(3)

Self-Timed Circuit Design*

519

(15)

Self-Timed Logic---An Asynchronous Technique

519

(3)

Completion-Signal Generation

522

(4)

Self-Timed Signaling

526

(5)

Practical Examples of Self-Timed Logic

531

(3)

Synchronizers and Arbiters*

534

(5)

Synchronizers---Concept and Implementation

534

(4)

Arbiters

538

(1)

Clock Synthesis and Synchronization Using a Phase-Locked Loop*

539

(7)

Basic Concept

540

(2)

Building Blocks of a PLL

542

(4)

Future Directions and Perspectives

546

(4)

Distributed Clocking Using DLLs

546

(2)

Optical Clock Distribution

548

(1)

Synchronous versus Asynchronous Design

549

(1)

Summary

550

(1)

To Probe Further

551

(2)

References

551

(2)

Design Methodology Insert G Design Verification

553

(168)

References

557

(2)

Designing Arithmetic Building Blocks

559

(64)

Introduction

560

(1)

Datapaths in Digital Processor Architectures

560

(1)

The Adder

561

(25)

The Binary Adder: Definitions

561

(3)

The Full Adder: Circuit Design Considerations

564

(7)

The Binary Adder: Logic Design Considerations

571

(15)

The Multiplier

586

(8)

The Multiplier: Definitions

586

(1)

Partial-Product Generation

587

(2)

Partial-Product Accumulation

589

(4)

Final Addition

593

(1)

Multiplier Summary

594

(1)

The Shifter

594

(2)

Barrel Shifter

595

(1)

Logarithmic Shifter

596

(1)

Other Arithmetic Operators

596

(4)

Power and Speed Trade-offs in Datapath Structures*

600

(18)

Design Time Power-Reduction Techniques

601

(10)

Run-Time Power Management

611

(6)

Reducing the Power in Standby (or Sleep) Mode

617

(1)

Perspective: Design as a Trade-off

618

(1)

Summary

619

(1)

To Probe Further

620

(3)

References

621

(2)

Designing Memory and Array Structures

623

(98)

Introduction

624

(10)

Memory Classification

625

(2)

Memory Architectures and Building Blocks

627

(7)

The Memory Core

634

(38)

Read-Only Memories

634

(13)

Nonvolatile Read-Write Memories

647

(10)

Read-Write Memories (RAM)

657

(13)

Contents-Addressable or Associative Memory (CAM)

670

(2)

Memory Peripheral Circuitry*

672

(21)

The Address Decoders

672

(7)

Sense Amplifiers

679

(7)

Voltage References

686

(3)

Drivers/Buffers

689

(1)

Timing and Control

689

(4)

Memory Reliability and Yield*

693

(8)

Signal-to-Noise Ratio

693

(5)

Memory Yield

698

(3)

Power Dissipation in Memories*

701

(6)

Sources of Power Dissipation in Memories

701

(1)

Partitioning of the Memory

702

(1)

Addressing the Active Power Dissipation

702

(2)

Data-Retention Dissipation

704

(3)

Summary

707

(1)

Case Studies in Memory Design

707

(7)

The Programmable Logic Array (PLA)

707

(3)

A 4-Mbit SRAM

710

(2)

A 1-Gbit NAND Flash Memory

712

(2)

Perspective: Semiconductor Memory Trends and Evolutions

714

(2)

Summary

716

(1)

To Probe Further

717

(4)

References

718

(3)

Design Methodology Insert H Validation and Test of Manufactured Circuits

721

(18)

Introduction

721

(1)

Test Procedure

722

(1)

Design for Testability

723

(11)

Issues in Design for Testability

723

(2)

Ad Hoc Testing

725

(1)

Scan-Based Test

726

(3)

Boundary-Scan Design

729

(1)

Built-in Self-Test (BIST)

730

(4)

Test-Pattern Generation

734

(3)

Fault Models

734

(2)

Automatic Test-Pattern Generation (ATPG)

736

(1)

Fault Simulation

737

(1)

To Probe Further

737

(2)

References

737

(2)

Problem Solutions

739

(6)

Index

745

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Digital Integrated Circuits

Summary

Table of Contents

Supplemental Materials