2000 IEEE Symposium on Field-Programmable Custom Computing Machines : Proceedings: April 17-19, 2000, Napa Valley, California

, by IEEE Symposium on FPGAs for Custom Computing Machines (2000 : Napa Valley, Calif.); Hutchings, Brad L.; Hutchings, Brad L.

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ISBN: 9780769508719 | 0769508715
Cover: Paperback
Copyright: 12/1/2000

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Conference Organizers

Session 1: Architecture

Andre DeHon

Design of a VLIW Compute Accelerator on the Transmogrifier-2

(10)

L. Zhang

Q. Wang

D. Lewis

A Scalable, Loadable Custom Programmable Logic Device for Solving Boolean Satisfiability Problems

(9)

M. Boyd

T. Larrabee

Configuration Caching Management Techniques for Reconfigurable Computing

(17)

Z. Li

K. Compton

S. Hauck

Session 2: Compilation 1

Wayne Luk

A MATLAB Compiler for Distributed, Heterogeneous, Reconfigurable Computing Systems

(10)

P. Banerjee

N. Shenoy

A. Choudhary

S. Hauck

C. Bachmann

M. Haldar

P. Joisha

A. Jones

A. Kanhare

A. Nayak

S. Periyacheri

M. Walkden

D. Zaretsky

Stream-Oriented FPGA Computing in the Streams-C High Level Language

(10)

M. Gokhale

J. Stone

J. Arnold

M. Kalinowski

Session 3: Applications 1

Philip Freiden

A Reconfigurable Computing Architecture for Microsensors

(9)

S. Scalera

M. Falco

B. Nelson

FPGA Implementation of a Microcoded Elliptic Curve Cryptographic Processor

(9)

K. Leung

K. Ma

W. Wong

P. Leong

Customizing Graphics Applications: Techniques and Programming Interface

(14)

H. Styles

W. Luk

Session 4: Compilation 2

Scott Hauck

Automatic Synthesis of Data Storage and Control Structures for FPGA-Based Computing Engines

(10)

P. Diniz

J. Park

A C to HDL Compiler for Pipeline Processing on FPGAs

101

(12)

T. Maruyama

T. Hoshino

Session 5: Cryptographic Applications

John McHenry

High Performance DES Encryption in Virtex™ FPGAs Using Jbits™

113

(9)

C. Patterson

A Bit-Serial Implementation of the International Data Encryption Algorithm IDEA

122

(10)

M. Leong

O. Cheung

K. Tsoi

P. Leong

An Adaptive Cryptographic Engine for IPSec Architectures

132

(13)

A. Dandalis

V. Prasanna

J. Rolim

Session 6: Programming Tools

Brad Hutchings

Death of the RLOC?

145

(8)

S. Singh

Automated Extraction of Run-Time Parameterizable Cores from Programmable Device Configurations

153

(12)

P. James-Roxby

S. Guccione

Session 7: Fault Tolerance

Philip Kuekes

Dynamic Fault Tolerance in FPGAs via Partial Reconfiguration

165

(10)

J. Emmert

C. Stroud

B. Skaggs

M. Abramovici

An ACS Robotic Control Algorithm with Fault Tolerant Capabilities

175

(10)

S-Y. Yu

N. Saxena

E. McCluskey

Tunable Fault Tolerance for Runtime Reconfigurable Architectures

185

(10)

S. Sinha

P. Kamarchik

S. Goldstein

Session 8: Wireless Applications

Tom Kean

Synchronization in Software Radios--Carrier and Timing Recovery Using FPGAs

195

(10)

C. Dick

F. Harris

M. Rice

Architecture and Application of a Dynamically Reconfigurable Hardware Array for Future Mobile Communication Systems

205

(12)

A. Alsolaim

J. Becker

M. Glesner

J. Starzyk

Session 9: Applications 2

Mike Butts

Implementation of Near Shannon Limit Error-Correcting Codes Using Reconfigurable Hardware

217

(10)

B. Levine

R. Taylor

H. Schmit

Hardware-Software Codesign and Parallel Implementation of a Golomb Ruler Derivation Engine

227

(9)

E. Sotiriades

A. Dollas

P. Athanas

An FPGA-Based Coprocessor for the Parsing of Context-Free Grammars

236

(13)

C. Ciressan

E. Sanchez

M. Rajman

J-C. Chappelier

Session 10: Applications 3

Don Bouldin

A Reliable LZ Data Compressor on Reconfigurable Coprocessors

249

(10)

W-J. Huang

N. Saxena

E. McCluskey

Evidence: An FPGA-Based System for Photon EVent IDENtification and CEntroiding

259

(8)

M. Alderighi

S. D'Angelo

G. Sechi

Improving the Performance and Efficiency of an Adaptive Amplification Operation Using Configurable Hardware

267

(12)

M. Wirthlin

S. Morrison

P. Graham

B. Bray

Poster Session 1

Configuration Relocation and Defragmentation for Reconfigurable Computing

279

(2)

K. Compton

J. Cooley

S. Knol

S. Hauck

Mapping Algorithms for a Multi-Bit Data Path Processing Reconfigurable Chip RHW

281

(2)

T. Yamauchi

S. Nakaya

T. Inuo

N. Kajihara

Hardware Accelerator for Subgraph Isomorphism Problems

283

(2)

S. Ichikawa

L. Udorn

K. Konishi

A Reconfigurable Hardware Platform for Digital Real-Time Signal Processing in Television Studios

285

(2)

K. Henriss

P. Ruffer

R. Ernst

S. Hasenzahl

Reconfigurable Array Media Processor (RAMP)

287

(2)

K. Rath

S. Tangirala

P. Friel

P. Bolsara

J. Flores

J. Wadley

Internet Connected FPGAs

289

(2)

H. Fallside

M. Smith

A Reconfigurable Stochastic Model Simulator for analysis of parallel systems

291

(4)

O. Yamamoto

Y. Shibata

H. Kurosawa

H. Amano

Poster Session 2

A Virtual Hardware System on a Dynamically Reconfigurable Logic Device

295

(2)

Y. Shibata

M. Uno

H. Amano

K. Furuta

T. Fujii

M. Motomura

Optimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable Architectures

297

(2)

R. Maestre

F. Kurdahi

M. Fernandez

R. Hermida

N. Bagherzadeh

H. Singh

A Communication Scheduling Algorithm For Multi-FPGA Systems

299

(2)

J. Suh

D-I. Kang

S. Crago

Preemptive Multitasking on FPGAs

301

(2)

L. Levinson

R. Manner

M. Sessler

H. Simmler

BigSky--An On-Line Arithmetic Design Tool for FPGAs

303

(2)

A. Schneider

R. McIlhenny

M. Ercegovac

Improving the FPGA Design Process through Determining and Applying Logical-to-Physical Design Mappings

305

(2)

P. Graham

B. Hutchings

B. Nelson

Multiple Precision for Resource Minimization

307

(2)

G. Constantinides

P. Cheung

W. Luk

StReAm: Object-Oriented Programming of Stream Architectures Using PAM-Blox

309

(4)

O. Mencer

H. Hubert

M. Morf

M. Flynn

Poster Session 3

An FPGA-Based Array Processor for an Ionospheric-Imaging Radar

313

(2)

T. Tuan

M. Figueroa

F. Lind

X. Zhou

X. Diorio

J. Sahr

Embedded Compilation for Multimedia Applications

315

(2)

N. Daw

S. Goldstein

D. Strelow

Interfacing Reconfigurable Logic with a CPU

317

(2)

K. Walker

M. Budiu

S. Goldstein

A Run-Time Reconfigurable Plug-In for the Winamp MP3 Player

319

(2)

J. Scalera

M. Jones

Accelerating Embedded Applications Using Dynamically Reconfigurable Hardware and Evolutionary Algorithms

321

(2)

J. Harkin

T. McGinnity

L. Maguire

Implementation of a Configurable Controller for an AC Drive Control: A Case Study

323

(2)

M. Imecs

P. Bikfalvi

S. Nedevschi

J. Vasarhelyi

Pattern Recognition and Reconstruction on an FPGA Coprocessor Board

325

(4)

R. Manner

M. Sessler

H. Simmler

Poster Session 4

FCCMs and the Memory Wall

329

(2)

S. Derrien

S. Rajopadhye

A C to Hardware/Software Compiler

331

(2)

K. Bazargan

R. Kastner

S. Ogrenci

M. Sarrafzadeh

Evaluating Hardware Compilation Techniques

333

(2)

M. Weinhardt

W. Luk

Adapting Constant Multipliers in a Neural Network Implementation

335

(2)

P. James-Roxby

B. Blodget

A Networked FPGA-Based Hardware Implementation of a Neural Network Application

337

(2)

H. Restrepo

R. Hoffmann

A. Perez-Uribe

C. Teuscher

E. Sanchez

Design of C++ Class Library and Bit-Serial Compiler for Variable-Precision Datapath Synthesis on Adaptive Computing Systems

339

(2)

K. Suzuki

M. Wang

F. Zhao

W. Dai

An Investigation of Reconfigurable Multipliers for Use in Adaptive Signal Processing

341

(3)

T. Courtney

R. Turner

R. Woods

Combining Serialization and Reconfiguration for Convolver Designs

344

(3)

A. Derbyshire

W. Luk

Author Index

347

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2000 IEEE Symposium on Field-Programmable Custom Computing Machines : Proceedings: April 17-19, 2000, Napa Valley, California

Table of Contents

Supplemental Materials

FREE SHIPPING

Rent More, Save More! Use code: BBRENTAL

5% off 1 book, 7% off 2 books, 10% off 3+ books

2000 IEEE Symposium on Field-Programmable Custom Computing Machines : Proceedings: April 17-19, 2000, Napa Valley, California

Table of Contents

Supplemental Materials

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