40th IEEE/Acm International Symposium on Microarchitecture (Micro 2007)

, by Institute of Electrical and Electronics Engineers

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ISBN: 9780769530475 | 0769530478
Cover: Paperback
Copyright: 6/7/2008

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Supplemental Materials

Optimizing NUCA organizations and wiring alternatives for large caches with CACTI 6.0	p. 3
Process variation tolerant 3T1D-based cache architectures	p. 15
Mitigating parameter variation with dynamic fine-grain body biasing	p. 27
Optimal versus heuristic global code scheduling	p. 43
Global multi-threaded instruction scheduling	p. 56
Revisiting the sequential programming model for multi-core	p. 69
Penelope : the NBTI-aware processor	p. 85
Software-based online detection of hardware defects : mechanisms, architectural support, and evaluation	p. 97
Self-calibrating online wearout detection	p. 109
Implementing signatures for transactional memory	p. 123
Smart refresh : an enhanced memory controller design for reducing energy in conventional and 3D die-stacked DRAMs	p. 134
Stall-time fair memory access scheduling for chip multiprocessors	p. 146
Impact of cache coherence protocols on the processing of network traffic	p. 161
Flattened butterfly topology for on-chip networks	p. 172
Using address independent seed encryption and bonsai Merkle trees to make secure processors OS- and performance-friendly	p. 183
Multi-bit error tolerant caches using two-dimensional error coding	p. 197
Argus : low-cost, comprehensive error detection in simple cores	p. 210
Leveraging 3D technology for improved reliability	p. 223
Effective optimistic-checker tandem core design through architectural pruning	p. 236
FPGA-accelerated simulation technologies (FAST) : fast, full-system, cycle-accurate simulators	p. 249
Microarchitectural design space exploration using an architecture-centric approach	p. 262
Informed microarchitecture design space exploration using workload dynamics	p. 274
Time interpolation : so many metrics, so few registers	p. 286
Low-cost epoch-based correlation prefetching for commercial applications	p. 301
A framework for coarse-grain optimizations in the on-chip memory hierarchy	p. 314
Uncorq : unconstrained snoop request delivery in embedded-ring multiprocessors	p. 327
A framework for providing quality of service in chip multi-processors	p. 343
A practical approach to exploiting coarse-grained pipeline parallelism in C programs	p. 356
Data access partitioning for fine-grain parallelism on multicore architectures	p. 369
Composable lightweight processors Changkyu Kim Simha Sethumadhavan	p. 381
The art of deception : adaptive precision reduction for area efficient physics acceleration	p. 394
Dynamic warp formation and scheduling for efficient GPU control flow	p. 407
Scavenger : a new last level cache architecture with global block priority	p. 421
Guaranteeing hits to improve the efficiency of a small instruction cache	p. 433
Emulating optimal replacement with a shepherd cache	p. 445
Author index	p. 455
Table of Contents provided by Blackwell. All Rights Reserved.

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40th IEEE/Acm International Symposium on Microarchitecture (Micro 2007)

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40th IEEE/Acm International Symposium on Microarchitecture (Micro 2007)

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