CMOS Sigma-Delta Converters Practical Design Guide

Dr Rocío del Río, Institute of Microelectronics of Seville, IMSE-CNM (CSIC and University of Seville), Spain
Rocío del Río joined the Department of Electronics and Electromagnetism at the University of Seville in 1995, where she currently is an Associate Professor. She has also been with the Institute of Microelectronics of Seville of the Spanish Microelectronics Center since 1995. Her main research interests are in the field of mixed-signal integrated circuit design, especially sigma-delta analog-to-digital converters, including analysis, modeling, and computer-aided design. She has participated in several national and European R&D projects and has co-authored more than 90 international scientific publications, including journal and conference papers, book chapters and the book CMOS Cascade Sigma-Delta Modulators for Sensors and Telecom: Error Analysis and Practical Design (Springer, 2006).

List of Abbreviations xv

Preface xix

References xxiii

Acknowledgements xxv

1 Introduction to _Modulators: Basic Concepts and Fundamentals 1

1.1 Basics of A/D Conversion 1

1.1.1 Sampling 2

1.1.2 Quantization 3

1.1.3 Quantization White Noise Model 4

1.1.4 Noise Shaping 6

1.2 Basics of Sigma-Delta Modulators 8

1.2.1 Topology of __ ADCs 8

1.2.2 Signal Processing in __Ms 9

1.2.3 Performance Metrics of __Ms 10

1.2.4 Performance Enhancement of __Ms 13

1.3 Classification of __ Modulators 15

1.4 Single-Loop __ Modulators 16

1.4.1 Second-Order __M 16

1.4.2 High-Order __Ms 20

1.5 Cascade __ Modulators 24

1.6 Multibit __ Modulators 28

1.6.1 Influence of Multibit DAC Errors 29

1.6.2 DEM Techniques 31

1.6.3 Dual Quantization 34

1.7 Band-Pass __ Modulators 35

1.7.1 The z ! ��z2 LP–BP Transformation 37

1.7.2 BP-__Ms with Optimized NTF 39

1.8 Continuous-Time __ Modulators 40

1.8.1 DT–CT Transformation of __Ms 43

1.8.2 Direct Synthesis of CT-__Ms 48

1.9 Summary 48

References 49

2 Circuits and Errors: Systematic Analysis and Practical Design Issues 53

2.1 Nonidealities in Switched-Capacitor __ Modulators 54

2.2 Finite Amplifier Gain in SC-__Ms 55

2.3 Capacitor Mismatch in SC-__Ms 59

2.4 Integrator Settling Error in SC-__Ms 61

2.4.1 Behavioral Model for the Integrator Settling 61

2.4.2 Linear Effect of Finite Amplifier Gain-Bandwidth Product 66

2.4.3 Nonlinear Effect of Finite Amplifier Slew Rate 67

2.4.4 Effect of Finite Switch On-Resistance 67

2.5 Circuit Noise in SC-__Ms 70

2.6 Clock Jitter in SC-__Ms 74

2.7 Sources of Distortion in SC-__Ms 75

2.7.1 Nonlinear Amplifier Gain 75

2.7.2 Nonlinear Switch On-Resistance 77

2.8 Nonidealities in Continuous-Time __ Modulators 79

2.9 Clock Jitter in CT-__Ms 80

2.9.1 Jitter in Return-to-Zero DACs 81

2.9.2 Jitter in NonReturn-to-Zero DACs 82

2.9.3 Jitter in Switched-Capacitor DACs 83

2.10 Excess Loop Delay in CT-__Ms 84

2.11 Quantizer Metastability in CT-__Ms 87

2.12 Finite Amplifier Gain in CT-__Ms 88

2.13 Time-Constant Error in CT-__Ms 90

2.14 Finite Integrator Dynamics in CT-__Ms 93

2.15 Circuit Noise in CT-__Ms 93

2.16 Sources of Distortion in CT-__Ms 95

2.16.1 Nonlinearities in the Front-End Integrator 95

2.16.2 Intersymbol Interference in the Feedback DAC 96

2.17 Case Study: High-Level Sizing of a __M 97

2.18 Summary 105

References 105

3 Behavioral Modeling and High-Level Simulation 109

3.1 Systematic Design Methodology of __ Modulators 109

3.1.1 System Partitioning and Abstraction Levels 109

3.1.2 Sizing Process 111

3.2 Simulation Approaches for the High-Level Evaluation of __Ms 112

3.2.1 Alternatives to Transistor-Level Simulation 113

3.2.2 Event-Driven Behavioral Simulation Technique 115

3.2.3 Programming Languages and Behavioral Modeling Platforms 115

3.3 Implementing __M Behavioral Models 117

3.3.1 From Circuit Analysis to Computational Algorithms 117

3.3.2 Time-Domain versus Frequency-Domain Behavioral Models 120

3.3.3 Implementing Time-Domain Behavioral Models in MATLAB 123

3.3.4 Building Time-Domain Behavioral Models as SIMULINK C-MEX S-functions 127

3.4 Efficient Behavioral Modeling of __M Building Blocks using C-MEX Sfunctions 132

3.4.1 Modeling of SC Integrators using S-functions 135

3.4.2 Modeling of CT Integrators using S-functions 146

3.4.3 Behavioral Modeling of Quantizers using S-functions 151

3.5 SIMSIDES: A SIMULINK-Based Behavioral Simulator for __Ms 156

3.5.1 Model Libraries Included in SIMSIDES 158

3.5.2 Structure of SIMSIDES and User Interface 159

3.6 Using SIMSIDES for the High-Level Sizing and Verification of __Ms 164

3.6.1 SC Second-Order Single-Bit __M 165

3.6.2 CT Fifth-order Cascade 3-2 Multibit __M 175

3.7 Summary 182

References 183

4 Circuit-Level Design, Implementation, and Verification 187

4.1 Macromodeling __Ms 188

4.1.1 SC Integrator Macromodel 188

4.1.2 CT Integrator Macromodel 190

4.1.3 Nonlinear OTA Transconductor 191

4.1.4 Embedded Flash ADC Macromodel 192

4.1.5 Feedback DAC Macromodel 193

4.1.6 Examples of __M Macromodels 196

4.2 Including Noise in Transient Electrical Simulations of __Ms 200

4.2.1 Generating and Injecting Noise Data Sequences in HSPICE 201

4.2.2 Analyzing the Impact of Main Noise Sources in SC Integrators 204

4.2.3 Generating and Injecting Flicker Noise Sources in Electrical Simulations 205

4.2.4 Test Bench to Include Noise in the Simulation of __Ms 209

4.3 Processing __M Output Results of Electrical Simulations 211

4.4 Design Considerations and Simulation Test Benches of __MBasic Building Blocks 214

4.4.1 Design Considerations of CMOS Switches 215

4.4.2 Design Considerations of Operational Amplifiers 223

4.4.3 Design Considerations of Transconductors 231

4.4.4 Design Considerations of Comparators 236

4.4.5 Design Considerations of Current-Steering DACs 245

4.5 Auxiliary __M Building Blocks 252

4.5.1 Clock-Phase Generators 253

4.5.2 Generation of Common-Mode Voltage, Reference Voltage, and Bias Currents 255

4.5.3 Additional Digital Logic 259

4.6 Layout Design, Floorplanning, and Practical Issues 259

4.6.1 Layout Floorplanning 260

4.6.2 I/O Pad Ring 262

4.6.3 Importance of Layout Verification and Catastrophic Failures 262

4.7 Chip Package, Test PCB, and Experimental Set-Up 264

4.7.1 Bonding Diagram and Package 265

4.7.2 Test PCB 267

4.7.3 Experimental Test Set-Up 269

4.8 Summary 272

References 273

5 Frontiers of __ Modulators: Trends and Challenges 277

5.1 Overview of the State-of-the-Art on __Ms 278

5.1.1 DR-versus-Bw Conversion Region 279

5.1.2 Conversion Energy and Figures of Merit 280

5.2 Empirical and Statistical Analysis of State-of-the-Art __Ms 283

5.2.1 SC versus CT State-of-the-Art __Ms 283

5.2.2 Gm-C versus Active-RC State-of-the-Art CT-__Ms 285

5.2.3 Technology used in State-of-the-Art __Ms 288

5.2.4 Single-Loop versus Cascade State-of-the-Art __Ms 288

5.2.5 Single-Bit versus Multibit State-of-the-Art __Ms 289

5.2.6 Low-Pass versus Band-Pass State-of-the-Art __Ms 290

5.3 Cutting-Edge __M Architectures and Techniques 293

5.3.1 SMASH __M Architectures 294

5.3.2 Hybrid __Ms 296

5.3.3 Multirate __Ms 300

5.3.4 Multibit __Ms with Time-Coded Quantization 303

5.3.5 Mostly Digital __Ms 305

5.3.6 Adaptive/Reconfigurable __Ms 307

5.3.7 Ultra-High-Speed CT-__Ms for RF Digitization 309

5.4 Classification of State-of-the-Art References 311

5.5 Summary 312

References 313

A SIMSIDES User Guide 339

A.1 Getting Started: Installing and Running SIMSIDES 339

A.2 Building and Editing __M Architectures in SIMSIDES 340

A.3 Analyzing __Ms in SIMSIDES 340

A.4 Example 351

A.5 Getting Help 358

B SIMSIDES Block Libraries and Models 361

B.1 Overview of SIMSIDES Libraries 361

B.2 Ideal Libraries 361

B.2.1 Ideal Integrators 361

B.2.2 Ideal Resonators 362

B.2.3 Ideal Quantizers 364

B.2.4 Ideal D/A Converters 366

B.3 Real SC Building-Block Libraries 367

B.3.1 Real SC Integrators 367

B.3.2 Real SC Resonators 371

B.4 Real SI Building-Block Libraries 373

B.4.1 Real SI Integrators 373

B.4.2 Real SI Resonators 375

B.4.3 SI Errors and Model Parameters 375

B.5 Real CT Building-Block Libraries 378

B.5.1 Real CT Integrators 379

B.5.2 Real CT Resonators 385

B.6 Real Quantizers & Comparators 389

B.7 Real D/A Converters 390

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