Design of High-Performance Microprocessor Circuits

, by Chandrakasan, Anantha; Bowhill, William J.; Fox, Frank

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ISBN: 9780780360013 | 078036001X
Cover: Hardcover
Copyright: 10/10/2000

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This book covers the design of next generation microprocessors in deep submicron CMOS technologies. The chapters in Design of High Performance Microprocessor Circuits were written by some of the world's leading technologists, designers, and researchers. All levels of system abstraction are covered, but the emphasis rests squarely on circuit design. Examples are drawn from processors designed at AMD, Digital/Compaq, IBM, Intel, MIPS, Mitsubishi, and Motorola.Each topic of this invaluable reference stands alone so the chapters can be read in any order. The following topics are covered in depth: Architectural constraints of CMOS VLSI design Technology scaling, low-power devices, SOI, and process variations Contemporary design styles including a survey of logic families, robust dynamic circuits, asynchronous logic, self-timed pipelines, and fast arithmetic units Latches, clocks and clock distribution, phase-locked and delay-locked loops Register file, cache memory, and embedded DRAM design High-speed signaling techniques and I/O design ESD, electromigration, and hot-carrier reliability CAD tools, including timing verification and the analysis of power distribution schemes Test and testabilityDesign of High-Performance Microprocessor Circuits assumes a basic knowledge of digital circuit design and device operation, and covers a broad range of circuit styles and VLSI design techniques. Packed with practical know-how, it is an indispensable reference for practicing circuit designers, architects, system designers, CAD tool developers, process technologists, and researchers. It is also an essential text for VLSI design courses.

Preface

xix

PART I OVERVIEW

(24)

Impact of Physical Technology on Architecture

(22)

John H. Edmondson

Introduction

(3)

Suitability of CMOS Technology

(1)

Physical Technology Impact at Various Scales

(1)

RISC and the Importance of Well-Chosen Architecture

(1)

Key High-Level Decisions and Trade-Offs

(1)

Other Technology Issues

(1)

Implementing Processor Architecture in CMOS Technology

(8)

Dynamic Logic

(3)

Advanced Logic Styles

(1)

Dynamic Logic Examples from High-Performance Processor Designs

(3)

Datapaths

(1)

RAMs

(2)

Choosing the Cycle Time of a High-Performance Microprocessor

(1)

Critical Loops

(1)

Comparison of PA8000, 21164, and 21264 Processors

(2)

Trend in Interconnect Resistance

(1)

Interconnect Inductance

(1)

Architectural Consequences of Interconnect Trends

(1)

Trend in Power Consumption

(3)

Power Estimation and Scaling

(2)

Energy-Delay Product

(1)

Physical Limits of Heat Dissipation

(1)

Active Power Control

(1)

Vdd Reduction

(1)

Ultimate Impact of Power

(1)

Advanced Packaging

(2)

Conclusion

(2)

References

(2)

PART II TECHNOLOGY ISSUES

(92)

CMOS Scaling and Issues in Sub-0.25 μm Systems

(19)

Yuan Taur

MOSFET Scaling Theory

(4)

Constant-Field Scaling

(2)

Two-Dimensional Scale Length Theory

(2)

CMOS Scaling Issues below 0.25 μm

(8)

Power Supply and Threshold Voltage

(4)

Gate Oxides

(1)

Channel Profile Design

(3)

Interconnect RC Delay

(3)

Interconnect Scaling

(2)

Global Wire Issues

(1)

Low-Temperature CMOS

(4)

References

(2)

Techniques for Leakage Power Reduction

(17)

Vivek De

Yibin Ye

Ali Keshavarzi

Siva Narendra

James Kao

Dinesh Somasekhar

Raj Nair

Shekhar Borkar

Introduction

(1)

Transistor Leakage Current Components

(5)

p-n Junction Reverse Bias Current (I1)

(1)

Weak Inversion (I2)

(1)

DIBL (I3)

(1)

GIDL (I4)

(1)

Punchthrough (I5)

(1)

Narrow Width Effect (I6)

(1)

Gate Oxide Tunneling (I7)

(1)

Hot Carrier Injection (I8)

(1)

Circuit Subthreshold Leakage Current

(3)

Transistor Stack Effect

(1)

Steady-State Leakage Model of Transistor Stacks

(2)

Transient Model of Transistor Stack Leakage

(1)

Leakage Control Techniques

(8)

Standby Leakage Control by Input Vector Activation

(2)

Embedded Dual-Vt Design for Domino Circuits

(1)

Adaptive Body Biasing

(3)

Acknowledgments

(1)

References

(2)

Low-Voltage Technologies

(17)

Tadahiro Kuroda

Takayasu Sakurai

Low-Voltage Low-Threshold-Voltage Circuit Design

(3)

Power, Energy, and Speed

(1)

Low-VDD, Low-VTH Design Space

(1)

Design Issues at Low VDD and Low VTH

(1)

Power-Down Scheme

(1)

Controlling VTH through Substrate Bias

(8)

Variable Threshold-Voltage CMOS (VTCMOS) Technology

(2)

VTCMOS Circuit Techniques

(2)

VTCMOS Performance and Penalty

(4)

Processor Design Examples

(3)

TX3900

(2)

SH-4

(1)

Conclusion

(2)

References

(1)

SOI Technology and Circuits

(18)

Ghavam G. Shahidi

Fari Assaderaghi

Dimitri Antoniadis

Introduction

(1)

Device Design Considerations for PD SOI versus FD SOI

(2)

Device Results

(4)

SOI Device Self-Heating

(1)

VT Variation Due to Floating Body

(3)

PD-SOI CMOS Digital Circuits

(8)

History Dependence of Propagation Delay

(3)

``Pass-Gate'' Transient Leakage

(1)

Circuit Issues in PD-SOI CMOS

(4)

SOI for Low Power

(1)

Conclusion

(2)

References

(2)

Models of Process Variations in Device and Interconnect

(19)

Duane Boning

Sani Nassif

Introduction: Sources of Variation

(1)

Overview: Statistical Descriptions

(3)

Lumped Statistics

(1)

Separation of Inter-Die and Intra-Die Variation

100

(1)

Inter-Die Variation

100

(1)

Intra-Die Variation

101

(1)

Survey of Process Variations

102

(3)

Device Geometry Variations

102

(1)

Device Material Parameter Variations

102

(1)

Device Electrical Parameter Variations

103

(1)

Interconnect Geometry Variations

103

(1)

Interconnect Material Parameter Variations

104

(1)

Methods to Characterize and Address Variation

105

(3)

Statistical Device Models

105

(1)

Sensitivity Analysis

106

(1)

Worst-Case Analysis

106

(1)

Spatial Variation Modeling and Mismatch

107

(1)

Application of Methods to Interconnect Impact Analysis

108

(6)

Example: Random and Wafer Level Variation Impact

109

(2)

Example: Interconnect Sensitivity Analysis

111

(1)

Example: Statistical Interconnect Impact

111

(1)

Example: Deterministic Interconnect Variation Impact

112

(2)

Conclusion

114

(3)

References

114

(3)

PART III CIRCUIT STYLES FOR LOGIC

117

(88)

Basic Logic Families

119

(21)

Kerry Bernstein

Introduction

119

(1)

Nonclocked Logic

119

(9)

Static Combinatorial CMOS Logic

120

(4)

DCVS

124

(1)

Pass-Gate Logic

125

(3)

Clocked Logic

128

(3)

Domino Logic--Single and Differential

128

(2)

Latched Evaluate Logic

130

(1)

Self-Timed and Asynchronous Logic

131

(2)

Self-Resetting CMOS

131

(1)

Clock-Delayed Domino

132

(1)

Implementation Issues

133

(5)

Circuit Style Selection Criteria

133

(4)

Design Metrics

137

(1)

Conclusion

138

(2)

Acknowledgments

138

(1)

References

138

(2)

Issues in Dynamic Logic Design

140

(18)

Paul Gronowski

Introduction to Dynamic Logic

140

(6)

Basics of Dynamic Logic

140

(2)

Examples of Dynamic Logic

142

(3)

Comparison of Dynamic Logic to Standard Complementary CMOS Logic

145

(1)

Design Issues with Dynamic Logic

146

(10)

Charge Leakage

146

(2)

Charge Sharing

148

(2)

Capacitive Coupling Issues

150

(3)

Minority Carrier Charge Injection

153

(2)

Supply Noise and Variation

155

(1)

Conclusion

156

(2)

References

157

(1)

Self-Timed Pipelines

158

(23)

Ted Williams

Introduction

158

(2)

Individual Stages

160

(3)

Definitions

163

(1)

Self-Timed Control Interconnections

164

(4)

Overall Pipeline Latency and Throughput

168

(5)

Ring Performance Graphs

169

(2)

Performance Region Edges

171

(2)

Applications

173

(3)

Margin, Testing, and Power Issues

176

(2)

Conclusion

178

(3)

References

179

(2)

High-Speed VLSI Arithmetic Units: Adders and Multipliers

181

(24)

Vojin G. Oklobdzija

Introduction

181

(1)

High-Speed Addition: Algorithms and VLSI Implementation

181

(12)

Full Adder

181

(2)

Ripple Carry Adder

183

(1)

Carry Skip Adder

183

(1)

Variable Block Adder

184

(1)

Carry Lookahead Adder

185

(5)

Recurrence Solver-Based Adders

190

(1)

Ling Adder

191

(1)

Conditional-Sum Addition

192

(1)

Carry Select Adder

192

(1)

DEC ``Alpha'' 21064 Adder

193

(1)

Multiplication

193

(9)

Algorithm

193

(2)

High-Performance Multipliers

195

(7)

Conclusion

202

(3)

References

203

(2)

PART IV CLOCKING

205

(78)

Clocked Storage Elements

207

(28)

Hamid Partovi

On Clocking Strategy

207

(2)

The Nonideal Nature of Clock Signals

209

(1)

Jitter

209

(1)

Skew

210

(1)

The Basic Latch-Pair

210

(1)

The Basic Flip-Flop

211

(2)

Rules for Robust Design--1

213

(2)

Timing Properties of Sequential Logic

215

(5)

Edge-Triggered Clocking

216

(1)

Level-Sensitive Clocking

217

(2)

Slack-Passing and Time-Borrowing

219

(1)

Two-Wire Non-Overlapping Clocks

220

(1)

Comparing Latch-Paris and Flip-Flops

220

(1)

High-Performance Clocked Storage Elements

221

(7)

The Modified Svensson Latch

222

(1)

The Transmission-Gate Level-Sensitive Latch

223

(1)

The Amplifier-Based Flip-Flop

223

(2)

The Latch and Flip-Flop Hybrid Element

225

(3)

Rules for Robust Design--2

228

(1)

Performance Metrics for Clocked Storage Elements

229

(2)

Latching Elements for Dynamic Circuits

231

(2)

Recommendations and Conclusion

233

(2)

References

233

(2)

Design of High-Speed CMOS PLLs and DLLs

235

(26)

John George Maneatis

Introduction

235

(1)

PLL Architectures

236

(2)

Loop Components

238

(1)

Delay-Locked Loops

238

(3)

DLL Frequency Response

239

(1)

DLL Design Strategy

240

(1)

Alternative DLL Structures

240

(1)

Phase-Locked Loops

241

(8)

PLL Frequency Response

242

(2)

PLL with Higher-Order Roll-Off

244

(3)

PLL Design Issues

247

(1)

PLL Design Strategy

248

(1)

Advanced PLL Architectures

249

(1)

DLL/PLL Performance Issues

250

(5)

Output Jitter

250

(1)

Causes of Jitter

251

(1)

Supply/Substrate Noise Response

252

(1)

Observations on Jitter

252

(1)

Minimizing Supply Noise Sensitivity

253

(1)

Supply Noise Filters

254

(1)

Minimizing Substrate Noise Sensitivity

254

(1)

DLL/PLL Circuits

255

(4)

VCDLs and VCOs

255

(2)

Phase Detectors

257

(1)

Charge Pumps

257

(1)

Loop Filters

258

(1)

Circuit Summary

259

(1)

Self-Biased Techniques

259

(1)

Conclusion

260

(1)

References

260

(1)

Clock Distribution

261

(22)

Daniel W. Bailey

Introduction

261

(4)

Definitions

262

(3)

Objectives

265

(3)

Ideal Clock Objectives

265

(1)

Evaluation of Objectives

266

(2)

Implementation

268

(5)

Final Stage Drivers

268

(1)

Predriver Network

269

(2)

Examples

271

(2)

Trends

273

(1)

Clock Driver Layout

273

(3)

Electromigration

275

(1)

Productivity

275

(1)

Yield

276

(1)

Variation

276

(3)

Process

276

(1)

Power Supply

277

(1)

Temperature

278

(1)

Data-Dependent Noise

279

(1)

Conclusion

279

(4)

References

280

(3)

PART V MEMORY SYSTEM DESIGN

283

(46)

285

(24)

Ronald Preston

Basic Architecture

286

(4)

General Purpose Registers

286

(1)

Single-Cycle Caches

286

(3)

Multicycle Cache Arrays

289

(1)

Basic SRAM Cell Design and Operation

290

(9)

Read Operation

291

(3)

Write Operation

294

(3)

Variants on the Basic 6T Cells

297

(2)

Address Path Design

299

(2)

Preliminary Decoders

299

(1)

Final Row Drivers

299

(1)

Word Line Hierarchies and Layout

300

(1)

Read Path Design

301

(4)

Twisted Bit Line Architectures

301

(1)

Bit Line Precharging

301

(1)

Column Multiplexing

302

(1)

Sense Amplifier Design

302

(2)

Hierarchical Read Paths

304

(1)

Write Path Design

305

(1)

Write Amplifier Design

305

(1)

Column Multiplexing

305

(1)

Redundancy

306

(1)

Implementing Redundancy

307

(1)

Reliability Issues

307

(2)

Alpha Particles and Cosmic Rays

307

(1)

References

308

(1)

Embedded Dram

309

(20)

Tadaaki Yamauchi

Michihiro Yamada

Introduction

309

(1)

DRAM Basis

309

(6)

DRAM Architecture

309

(1)

Memory Cell

310

(2)

Basic DRAM Core Operation

312

(2)

Memory Cell Array Architecture of Embedded DRAM

314

(1)

Voltage Generator

315

(4)

Basic Configuration

315

(1)

Back Bias Generator

316

(2)

Bit Line Precharge and Cell Plate Voltage Generators

318

(1)

Voltage-Down Converter

318

(1)

Embedded DRAM

319

(10)

Features

319

(1)

Recent Embedded DRAM LSIs

320

(1)

Process Issues of Embedded DRAM

321

(2)

Design Issues of Embedded DRAM

323

(3)

The Future of Embedded DRAM

326

(1)

References

327

(2)

PART VI INTERCONNECT AND I/O

329

(98)

Analyzing on-Chip Interconnect Effects

331

(21)

Noel Menezes

Lawrence Pileggi

Introduction

331

(4)

Process Scaling, Interconnect Scaling, and Noise

331

(1)

Local and Global Interconnect

332

(1)

Interconnect Modeling

332

(2)

The Duality between Noise and Delay

334

(1)

Simplified Interconnect Analysis

335

(3)

The Elmore Delay and Its Properties

335

(2)

A Noise Bound for Coupled Interconnect

337

(1)

Model Order Reduction

338

(8)

An Example

339

(1)

Calculating Moments

340

(2)

Moment Matching--AWE

342

(2)

Applying AWE to Delay and Noise Analysis

344

(1)

Other Model Order Reduction Techniques

345

(1)

Driver Models

346

(4)

Resistance Shielding

346

(1)

The Effective Capacitance Drive Model for RC Loads

347

(2)

N-Port Driver Models

349

(1)

Conclusion

350

(2)

References

350

(2)

Techniques for Driving Interconnect

352

(25)

Shannon V. Morton

Introduction

352

(1)

Technology Scaling Trends

352

(7)

Relative Spatial Dimensions

352

(4)

Faster Edge Rates

356

(1)

Longer Electrical Lengths On-Chip

357

(1)

Process Variation

358

(1)

Architectural Issues

358

(1)

Power Dissipation

359

(1)

Problems and Solutions Regarding Capacitance

359

(5)

Power Dissipation

360

(1)

Delay Variations

360

(1)

Crosstalk Noise

361

(1)

Potential Solutions

361

(3)

Problems and Solutions Regarding Inductance

364

(6)

Delay Variations

367

(1)

Crosstalk Noise

368

(1)

Potential Solutions

369

(1)

Problems and Solutions Regarding Resistance

370

(1)

Problems and Solutions Regarding Long Distance Routing

371

(4)

Repeater Insertion

371

(2)

Buffer Insertion

373

(1)

Low Swing Signaling

373

(1)

Active Regenerators

374

(1)

Current Sensing

374

(1)

Wave Pipelining

374

(1)

Conclusion

375

(2)

Acknowledgments

375

(1)

References

375

(2)

I/O and ESD Circuit Design

377

(20)

Stephen C. Thierauf

Warren R. Anderson

Introduction

377

(1)

Power Supply Considerations

378

(2)

Split Power Supply Systems

378

(1)

Power Supply Clamps

379

(1)

Off-Chip-Driver Edge Rate Control

380

(1)

Mixed-Voltage I/O

381

(3)

Floating Well Driver

381

(1)

Open Drain Signaling

382

(1)

Cascoding

383

(1)

Level Shifting

384

(1)

Impedance Matching

384

(1)

Precompensation Drivers

385

(1)

Input Receivers

385

(1)

The ESD Threat

386

(1)

ESD Models

387

(1)

Circuit Topology of the ESD Protection Network

388

(1)

The Qualities of Good ESD Protection

388

(1)

ESD Protection Design Elements and Methods

389

(4)

Nonsilicided and Silicide-Blocked NMOS

389

(1)

Silicided NMOS

390

(2)

Double Diode ESD Protection

392

(1)

Power Supply Clamps

393

(1)

CDM Considerations

394

(3)

References

395

(2)

High-Speed Electrical Signaling

397

(30)

Stefanos Sidiropoulos

Chih-Kong Ken Yang

Mark Horowitz

Transmission Lines

398

(4)

Image Currents

398

(1)

Reflections

399

(1)

Attenuation

400

(1)

Methods of Signaling

401

(1)

Link Performance Metrics

402

(3)

FO-4 Delay Metric

402

(1)

Link Margins

403

(2)

Transmitters

405

(5)

Output Drivers

406

(1)

Impedance, Current, and Slew-Rate Control

407

(2)

Maximizing Bit Rate

409

(1)

Receivers

410

(4)

Input Noise

411

(1)

Receiver Design

412

(1)

Demultiplexing Issues

413

(1)

Clock Generation

414

(4)

PLLs and Phase Noise

414

(2)

Dual-Loop Architectures

416

(1)

Timing Circuit Scaling

417

(1)

Future Trends

418

(4)

Equalization

419

(2)

Multilevel Signaling

421

(1)

DAC and ADCs

422

(1)

Conclusion

422

(5)

Acknowledgments

423

(1)

References

423

(4)

PART VII RELIABILITY

427

(40)

Electromigration Reliability

429

(20)

J. Joseph Clement

Introduction

429

(1)

Materials and Process Effects on Electromigration

430

(4)

Interconnect Technology Evolution

430

(1)

Effect of Interlevel Dielectrics

431

(1)

Microstructure, Line Width, and Line Length

432

(2)

Electromigration Lifetime

434

(5)

Electromigration Transport

434

(1)

Accelerated Lifetime Characterization

435

(1)

Modeling Electromigration

436

(1)

Pulsed dc and ac Operation

437

(2)

Designing for Electromigration Reliability

439

(6)

Reliability Budgeting

439

(1)

CAD Tools

439

(3)

CAD Reliability Analysis

442

(3)

rms Current Limits

445

(1)

Conclusion

445

(4)

Acknowledgments

446

(1)

References

446

(3)

Hot Carrier Reliability

449

(18)

Kaizad Mistry

What Are Hot Carriers?

449

(3)

How Do Hot Carriers Degrade MOSFETs?

452

(2)

Modeling the Degradation

454

(3)

Circuit Effects

457

(3)

Ensuring Circuit Reliability

460

(1)

Example Analysis

461

(2)

Transistor Scaling Trends

463

(4)

References

464

(3)

PART VIII CAD TOOLS AND TEST

467

(78)

Overview of Computer-Aided Design Tools

469

(11)

Yao-Tsung Yen

Introduction

469

(1)

Micro-Architecture Design and Circuit Feasibility Study Tools

470

(1)

RTL Model Design Tools

471

(2)

Datapath/Memory Design Tools

473

(2)

Datapath/Memory Schematic Design Tools

473

(2)

Datapath/Memory Layout Design Tools

475

(1)

Control Logic Design Tools

475

(1)

Chip Assembly and Global Net Route

476

(1)

Chip-Level Layout, Circuit, and Timing Verification

476

(2)

Layout Verification

476

(1)

Circuit and Timing Analysis

477

(1)

Test Patterns Generation

478

(1)

Conclusion

478

(2)

References

479

(1)

Timing Verification

480

(19)

Victor Peng

Introduction

480

(1)

Timing Verification Goals and Analysis

480

(4)

Speed (Set-Up Time) Analysis

480

(1)

Functional (Hold Time) Analysis

481

(1)

The Timing Analysis Process

482

(1)

Max Path Modeling

483

(1)

Min Path Modeling

483

(1)

Key Factors in High-Speed Design and Timing Verification

484

(6)

Product Goals

484

(1)

Clocking and Storage Element Strategy

484

(5)

Circut Structures and Design Guidelines

489

(1)

Timing Verification of Non-memory Custom Blocks

490

(2)

Dynamic Logic

490

(1)

Pass-Gate Logic

491

(1)

Self-Timed Logic

492

(1)

Timing Verification of Memory Blocks

492

(2)

Design Flow and Full-Chip Timing Verification

494

(3)

Future Challenges

497

(2)

References

498

(1)

Design and Analysis of Power Distribution Networks

499

(24)

David Blaauw

Rajendran Panda

Rajat Chaudhry

Introduction

499

(2)

Power Distribution Design

501

(9)

Power Grid Integrity Problems

501

(1)

Power Distribution Design Styles

502

(3)

Design Methodology for Power distribution Networks

505

(2)

Voltage Drop Mitigation

507

(2)

Power Grid Resonance

509

(1)

Power Distribution Analysis

510

(4)

Fast Linear Solvers for Power Grid Analysis

511

(1)

Simulation Vector Generation

512

(2)

Power Grid Models

514

(6)

Resistance Models for Power Networks

514

(1)

Capacitance Models for Power Networks

515

(2)

Inductance Models for Power Networks

517

(2)

Comparison between R, RC, and RLC Analysis

519

(1)

Conclusion

520

(3)

References

520

(3)

Testing of High-Performance Processors

523

(22)

Dilip K. Bhavsar

Introduction

523

(1)

Basic Concepts in Testing

524

(6)

Components of Testing

524

(1)

Fault Modeling and Testing Methods

525

(2)

Test Development

527

(2)

Testing in Production

529

(1)

Designing for Testability

530

(12)

Scan Design Techniques

530

(4)

Built-in Self-Test (BiST) Techniques

534

(6)

IEEE 1149.1 Standard Test Access Port and Boundary Scan Register

540

(2)

Conclusion

542

(3)

References

543

(2)

Index

545

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Design of High-Performance Microprocessor Circuits

Summary

Author Biography

Table of Contents

Supplemental Materials