A Designer's Guide to Asynchronous Vlsi

Create low power, higher performance circuits with shorter design times using this practical guide to asynchronous design. This practical alternative to conventional synchronous design enables performance close to full-custom designs with design times that approach commercially available ASIC standard cell flows. It includes design trade-offs, specific design examples, and end-of-chapter exercises. Emphasis throughout is placed on practical techniques and real-world applications, making this ideal for circuit design students interested in alternative design styles and system-on-chip circuits, as well as circuit designers in industry who need new solutions to old problems.

Peter A. Beerel is CEO of TimeLess Design Automation - his own company commercializing asynchronous VLSI tools and libraries - and an Associate Professor in the Electrical Engineering Department at the University of Southern California (USC). Dr. Beerel has 15 years' experience of research and teaching in asynchronous VLSI and has received numerous awards including the VSoE Outstanding Teaching Award in 1997 and the 2008 IEEE Region 6 Outstanding Engineer Award for significantly advancing the application of asynchronous circuits to modern VLSI chips. Recep O. Ozdag is IC Design Manager at Fulcrum Microsystems and a part-time Lecturer at USC, where he received his Ph.D. in 2004. Marcos Ferretti is one of the founders of PST Electronica S.A. (Positron), Brazil - an automotive electronic systems manufacturing company, where he is currently the Vice-President of Technology. He received his Ph.D. from USC in 2004 and was co-recipient of the USC Electrical Engineering-Systems Best Paper Award in the same year.

Acknowledgments	p. xi
Introduction	p. 1
Synchronous design basics	p. 2
Challenges in synchronous design	p. 4
Asynchronous design basics	p. 5
Asynchronous design flows	p. 6
Potential advantages of asynchronous design	p. 7
Challenges in asynchronous design	p. 10
Organization of the book	p. 11
Channel-based asynchronous design	p. 16
Asynchronous channels	p. 16
Sequencing and concurrency	p. 24
Asynchronous memories and holding state	p. 30
Arbiters	p. 33
Design examples	p. 36
Exercises	p. 40
Modeling channel-based designs	p. 43
Communicating sequential processes	p. 44
Using asynchronous-specific languages	p. 46
Using software programming languages	p. 47
Using existing hardware design languages	p. 47
Modeling channel communication in Verilog	p. 48
Implementing VerilogCSP macros	p. 55
Debugging in VerilogCSP	p. 58
Summary of VerilogCSP macros	p. 61
Exercises	p. 62
Pipeline performance	p. 66
Block metrics	p. 67
Linear pipelines	p. 69
Pipeline loops	p. 73
Forks and joins	p. 79
More complex pipelines	p. 81
Exercises	p. 82
Performance analysis and optimization	p. 84
Petri nets	p. 84
Modeling pipelines using channel nets	p. 88
Performance analysis	p. 90
Performance optimization	p. 96
Advanced topic: stochastic performance analysis	p. 100
Exercises	p. 102
Deadlock	p. 106
Deadlock caused by incorrect circuit design	p. 107
Deadlock caused by architectural token mismatch	p. 108
Deadlock caused by arbitration	p. 110
A taxonomy of design styles	p. 116
Delay models	p. 116
Timing constraints	p. 118
Input-output mode versus fundamental mode	p. 119
Logic styles	p. 119
Datapath design	p. 123
Design flows: an overview of approaches	p. 129
Exercises	p. 132
Synthesis-based controller design	p. 136
Fundamental-mode Huffman circuits	p. 136
STG-based design	p. 146
Exercises	p. 149
Micropipeline design	p. 152
Two-phase micropipelines	p. 152
Four-phase micropipelines	p. 159
True-four-phase pipelines	p. 162
Delay line design	p. 164
Other micropipeline techniques	p. 168
Exercises	p. 169
Syntax-directed translation	p. 172
Tangram	p. 173
Handshake components	p. 174
Translation algorithm	p. 176
Control component implementation	p. 177
Datapath component implementations	p. 178
Peephole optimizations	p. 187
Self-initialization	p. 188
Testability	p. 189
Design examples	p. 192
Summary	p. 196
Exercises	p. 197
Quasi-delay-insensitive pipeline templates	p. 200
Weak-conditioned half buffer	p. 200
Precharged half buffer	p. 204
Precharged full buffer	p. 216
Why input-completion sensing?	p. 217
Reduced-stack precharged half buffer (RSPCHB)	p. 220
Reduced-stack precharged full buffer (RSPCFB)	p. 229
Quantitative comparisons	p. 232
Token insertion	p. 232
Arbiter	p. 236
Exercises	p. 238
Timed pipeline templates	p. 240
Williams' PS0 pipeline	p. 240
Lookahead pipelines overview	p. 242
Dual-rail lookahead pipelines	p. 242
Single-rail lookahead pipelines	p. 247
High-capacity pipelines (single-rail)	p. 250
Designing non-linear pipeline structures	p. 253
Lookahead pipelines (single-rail)	p. 255
Lookahead pipelines (dual-rail)	p. 257
High-capacity pipelines (single-rail)	p. 259
Conditionals	p. 262
Loops	p. 263
Simulation results	p. 264
Summary	p. 266
Single-track pipeline templates	p. 267
Introduction	p. 267
GasP bundled data	p. 269
Pulsed logic	p. 270
Single-track full-buffer template	p. 271
STFB pipeline stages	p. 275
STFB standard-cell implementation	p. 283
Back-end design flow and library development	p. 290
The evaluation and demonstration chip	p. 290
Conclusions and open questions	p. 299
Exercises	p. 300
Asynchronous crossbar	p. 304
Fulcrum's Nexus asynchronous crossbar	p. 305
Clock domain converter	p. 309
Design example: the Fano algorithm	p. 313
The Fano algorithm	p. 313
The asynchronous Fano algorithm	p. 321
An asynchronous semi-custom physical design flow	p. 329
Index	p. 336
Table of Contents provided by Ingram. All Rights Reserved.

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A Designer's Guide to Asynchronous Vlsi

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