Digital Microfluidic Biochips: Synthesis,

Digital Microfluidic Biochips focuses on the automated design and production of microfluidic-based biochips for large-scale bioassays and safety-critical applications. Bridging areas of electronic design automation with microfluidic biochip research, the authors present a system-level design automation framework that addresses key issues in the design, analysis, and testing of digital microfluidic biochips.The book describes a new generation of microfluidic biochips with more complex designs that offer dynamic reconfigurability, system scalability, system integration, and defect tolerance. Part I describes a unified design methodology that targets design optimization under resource constraints. Part II investigates cost-effective testing techniques for digital microfluidic biochips that include test resource optimization and fault detection while running normal bioassays. Part III focuses on different reconfiguration-based defect tolerance techniques designed to increase the yield and dependability of digital microfluidic biochips.Expanding upon results from ongoing research on CAD for biochips at Duke University, this book presents new design methodologies that address some of the limitations in current full-custom design techniques. Digital Microfluidic Biochips is an essential resource for achieving the integration of microfluidic components in the next generation of system-on-chip and system-in-package designs.

Synthesis Techniques	p. 1
Introduction	p. 3
Technology Issues	p. 5
Biochip Technology	p. 5
Continuous-Flow Microfluidics	p. 6
Droplet-Based Microfluidics	p. 7
Digital Microfluidic Biochips	p. 11
Microfluidic Biochip Design Challenges	p. 13
Typical Design Methodology: Bottom-Up	p. 13
Top-Down Design Methodology	p. 14
Book Outline	p. 16
Architectural-Level Synthesis	p. 19
Background	p. 19
High-Level Synthesis Methodology	p. 20
Illustrative Example: Multiplexed in vitro Diagnostics	p. 20
Sequencing Graph Model	p. 22
Input Operations	p. 22
Mixing Operation	p. 23
Detection Operation	p. 24
Integer Linear Programming Model	p. 25
Dependency Constraints	p. 26
Resource Constraints	p. 26
Heuristics for the Scheduling Problem	p. 28
Simulation Experiments	p. 33
Evaluation Experiments	p. 34
Resource Selection	p. 35
Application to Protein Assay	p. 37
Summary	p. 39
Module Placement	p. 41
Background	p. 42
Module Placement Problem	p. 43
Fault Tolerance for Digital Microfluidic Biochips	p. 46
Partial Reconfiguration	p. 46
Fault Tolerance Index	p. 47
Fast Algorithm to Determine FTI	p. 47
Extending FTI to Multiple Faults	p. 50
Experimental Evaluation	p. 53
Example 1: PCR	p. 53
Example 2: Multiplexed in vitro Diagnostics	p. 58
Multiobjective Optimization Analysis	p. 63
Effect of [Beta]	p. 63
Pareto Optimization	p. 63
Summary	p. 65
Unified Synthesis Methodology	p. 67
Problem Formulation	p. 67
PRSA-Based Algorithm	p. 69
Representation of a Chromosome	p. 69
Construction Procedure	p. 70
Phase I: Resource Binding	p. 70
Phase II: Scheduling	p. 71
Phase III: Placement	p. 72
Enhancement for Defect Tolerance	p. 73
Experimental Evaluation	p. 75
Summary	p. 80
Droplet Routing	p. 81
Background	p. 81
Problem Formulation	p. 83
Objective Function	p. 83
Fluidic Constraints	p. 84
Timing Constraints	p. 86
Problem Decomposition	p. 87
Routing Method	p. 88
Phase I: M-Shortest Routes	p. 90
Two-Pin Nets	p. 90
Three-Pin Nets	p. 91
Phase II: Random Selection	p. 92
FCRC and Droplet Motion Modification	p. 92
Experimental Evaluation	p. 93
Summary	p. 97
Testing Techniques	p. 99
Testing Methodology	p. 101
Background	p. 101
Classification of Faults	p. 102
Unified Detection Mechanism	p. 103
Online Testing of Catastrophic Faults	p. 103
Parametric Fault Testing	p. 105
Fault-Free Model	p. 105
Lower-Bound Testing	p. 108
Upper-Bound Testing	p. 108
Evaluation of the Parametric Test Strategy	p. 110
Evaluation of Detectability	p. 111
Tolerance Analysis	p. 111
Minimum Detectable Deviations	p. 111
Simulation Experimental Setup	p. 113
Real-Time PCR in Digital Microfluidic Biochips	p. 113
Testing Parametric Faults in Biochips for PCR	p. 113
Insulator Degradation	p. 114
Particle Contamination	p. 114
Defect in Temperature Controller	p. 116
Summary	p. 117
Test Planning	p. 119
Problem Definition	p. 119
Analysis of Computational Complexity	p. 121
Integer Linear Programming Model for OPP	p. 123
Heuristic Algorithms	p. 126
Simple Monte Carlo Search Algorithm (SMC)	p. 127
Modified Real-Time Algorithm (MRT)	p. 127
Proposed Improved Heuristic Algorithm for Multiple Droplets (PIH-MD)	p. 128
Simulation Results	p. 129
Summary	p. 132
Concurrent Testing	p. 133
Concurrent Testing Methodology	p. 133
Optimal Scheduling for Concurrent Testing	p. 134
Testing Requirement	p. 135
Resource Constraint	p. 136
Starting Point	p. 136
Movement Rules	p. 136
Optimal Test Schedule	p. 137
Concurrent Testing Example	p. 140
Summary	p. 145
Defect-Oriented Testing and Diagnosis	p. 147
Fault Modeling	p. 148
Defect-Oriented Experiment	p. 149
Experiment Design	p. 149
Chip Fabrication and Experimental Setup	p. 149
Results and Analysis	p. 150
Testing and Diagnosis	p. 152
Offline Testing	p. 152
Online Testing	p. 157
Diagnosis	p. 158
Real-Life Application	p. 159
Summary	p. 162
Reconfiguration Techniques	p. 163
Reconfiguration Schemes	p. 165
Proposed Reconfiguration Schemes	p. 165
Local Reconfiguration Scheme	p. 165
Partial Reconfiguration Scheme	p. 166
Full Reconfiguration Scheme	p. 167
Example Evaluation	p. 168
Summary	p. 171
Defect Tolerance Based on Space Redundancy	p. 173
Background	p. 174
Microfluidic Array with Hexagonal Electrodes	p. 174
Defect-Tolerant Designs	p. 175
Estimation of Yield Enhancement	p. 178
Evaluation Example	p. 185
Summary	p. 190
Defect Tolerance Based on Graceful Degradation	p. 191
Tile-Based Architecture	p. 192
Clustered Defect Model	p. 192
Graceful Degradation with Reconfiguration	p. 193
Simulation Results	p. 197
Evaluation Example 1: PCR	p. 197
Evaluation Example 2: Multiplexed Diagnostics	p. 198
Summary	p. 201
Conclusions and Future Work	p. 203
Contributions of the Book	p. 203
Future Work	p. 205
Bibliography	p. 207
Index	p. 215
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Digital Microfluidic Biochips: Synthesis, Testing, and Reconfiguration Techniques

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