Hybrid Cmos Single-electron-transistor Device

CMOS (complementary metal oxide semiconductor) is a widely accepted and utilized technology among electrical engineers involved with circuit design. SET (single electron transistor) technology has recently gained significant attention, because it can be combined with CMOSs to improve overall performance of integrated circuits -- reducing power consumption and achieving greater functionality. This cutting-edge resource provides professionals with the conceptual framework and specific strategies for CMSO-SET hybrid circuit design. the book offers a thorough understanding of the pros and cons of digital SETs, and explains how SETs can solve the intrinsic drawbacks of CMOS technology. From the basic physics of single electron transistors and SET modeling, to advanced concepts like CMSO-SET co-integration, the book helps engineers realize significant performance benefits by showing them how to incorporate SET technology into their design projects.

Adrian Mihai Ionescu is head of the Laboratory of Micro and Nanoelectronic Devices and an associate professor at the Swiss Federal Institute of Technology, Lausanne, Switzerland.

Preface

xiii

Acknowledgments

xvii

1 Introduction: CMOS Scaling and Single Electronics

1

(14)

1.1 CMOS Scaling Limits

1

(4)

1.2 Emerging Nanotechnologies: Life After CMOS

5

(2)

1.3 Single-Electron Transistors—An Overview

7

(3)

1.4 Short History

10

(2)

References

12

(3)

2 Compact Modeling of SETs

15

(36)

2.1 Computer-Aided Design Tools for SET Simulation

15

(2)

2.2 Orthodox Theory of Single-Electron Tunneling

17

(1)

2.3 Carrier Transport in SET

18

(4)

2.4 Compact Modeling of SET

22

(10)

2.4.1 Assumptions

22

(1)

2.4.2 Tunneling Rate and Master Equation

23

(2)

2.4.3 Model Complexities: |VDS| Dependency

25

(2)

2.4.4 Development of the MIB Model

27

(3)

2.4.5 Simplified MIB Model

30

(2)

2.5 Model Verification

32

(5)

2.6 Subthreshold Slope

37

(6)

2.7 Parameter Extraction

43

(3)

2.8 Other SET Models

46

(1)

2.9 SET and MOSFET Modeling Technique A Comparison

47

(1)

2.10 Summary

47

(1)

References

48

(3)

3 Single-Electron Transistor Logic

51

(32)

3.1 Single-Electron Memory Versus Logic

51

(1)

3.2 SET Inverter Characteristics

52

(2)

3.3 Analysis of Inverter Characteristics

54

(9)

3.3.1 Zone 1

54

(5)

3.3.2 Zone 2

59

(1)

3.3.3 Zone 3

60

(1)

3.3.4 Zone 4

60

(3)

3.4 Estimation of Power Dissipation

63

(9)

3.4.1 Static Power Dissipation

63

(2)

3.4.2 Dynamic Power Dissipation

65

(1)

3.4.3 Temperature-Dependent Leakage Power Dissipation

66

(3)

3.4.4 Effect of Device Asymmetry on Power Dissipation

69

(1)

3.4.5 Effect of Background Charge on Power Dissipation

70

(2)

3.5 Propagation Delay of SET Inverter

72

(1)

3.6 Other Single-Electron Logic Gates

73

(7)

3.7 Comparison Between SET and CMOS Logic

80

(1)

3.8 Summary

80

(1)

References

81

(2)

4 Hybridization of CMOS and SET

83

(46)

4.1 Motivation for CMOS-SET Hybridization

83

(2)

4.2 Challenges for CMOS-SET Hybridization

85

(3)

4.2.1 CAD Framework for CMOS-SET Cosimulation and Codesign

86

(1)

4.2.2 Design Rules for Hybrid CMOS-SET Circuit Design

86

(2)

4.2.3 Technology for CMOS-SET Cofabrication

88

(1)

4.3 CMOS-SET Cosimulation and Codesign

88

(2)

4.3.1 Verilog-A Language

88

(2)

4.3.2 Implementation of MIB Model in Smartspice

90

(1)

4.4 Case Studies of Different Hybrid CMOS-SET Architectures

90

(16)

4.4.1 Neural Network

91

(2)

4.4.2 NDR and Hysteresis Architecture

93

(2)

4.4.3 Multiple Value Logic Circuit

95

(1)

4.4.4 Hybrid Digital-to-Analog and Analog-to-Digital Converters

96

(7)

4.4.5 Selective Multiband Voltage Filter

103

(1)

4.4.6 Automatic Oscillation Phase Controlled Set

104

(2)

4.5 SETMOS—Coulomb Blockade Oscillations in the Micro-Ampere Range

106

(15)

4.5.1 Architecture and Working Principle of SETMOS

108

(1)

4.5.2 Device Parameters and Operating Temperature

109

(1)

4.5.3 SETMOS Characteristics

110

(4)

4.5.4 SETMOS NDR Architecture

114

(3)

4.5.5 NEMS-SETMOS Architecture

117

(4)

4.6 Summary

121

(5)

References

126

(3)

5 Few Electron Multiple Valued Logic and Memory Design

129

(40)

5.1 Multiple Value Switching Algebra

129

(1)

5.2 Motivation for MV Logic Design

130

(4)

5.2.1 Interconnect Issues

130

(3)

5.2.2 Other Applications of MV Switching Algebra

133

(1)

5.3 Challenges for MVL Circuit Design

134

(8)

5.3.1 MVL Implementation in CMOS Technology

134

(2)

5.3.2 MVL Implementation in III-V Technology

136

(1)

5.3.3 Single-Electron MVL Design

137

(3)

5.3.4 Noise Margin Limitation in MVL Design

140

(2)

5.4 SETMOS Quaternary Logic

142

(12)

5.4.1 Literal and Universal Literal Gates

142

(7)

5.4.2 Transmission Gate (T-Gate)

149

(1)

5.4.3 Binary to Quaternary (B2Q) and Quaternary to Binary (Q2B) Converters

150

(4)

5.5 SETMOS Quaternary SRAM

154

(11)

5.5.1 Motivation and Challenges for MV Memory Design

154

(1)

5.5.2 MV Hysteresis Loop

155

(2)

5.5.3 SETMOS Quaternary SRAM Cell and Its Operation

157

(6)

5.5.4 Comparison Between CMOS and SETMOS Quaternary SRAM Cell

163

(2)

5.6 Summary

165

(1)

References

165

(4)

6 Fabrication of SETs and Compatibility with Silicon CMOS

169

(32)

6.1 Challenges of SET Fabrication

169

(4)

6.2 Single Island SET Fabrication

173

(12)

6.2.1 Pattern-Dependent Oxidation and V-PADOX

173

(6)

6.2.2 Other Fabrication Techniques for Single Island SET

179

(6)

6.3 Fabrication of Multi-Island SETs

185

(8)

6.4 Fabrication of CNTs and Molecular SETs

193

(4)

6.5 Summary

197

(2)

References

199

(2)

Appendix A Gibbs Free Energy and Development of MIB Model

201

(10)

A.1 Gibbs Free Energy for Single-Electron Systems

201

(1)

A.2 Calculation of AG for SET

202

(4)

A.2.1 Single-Electron Tunneling from Source to Island

203

(1)

A.2.2 Single-Electron Tunneling from Island to Source

204

(1)

A.2.3 Single-Electron Tunneling from Island to Drain

204

(1)

A.2.4 Single-Electron Tunneling from Drain to Island

205

(1)

A.3 Calculation of Drain Current in the MIB Model

206

(5)

Appendix B Transconductance and Conductance Analysis of the SET

211

(4)

B.1 Transconductance Analysis

211

(1)

B.2 Conductance Analysis

212

(3)

About the Authors

215

(2)

Index

217

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Hybrid Cmos Single-electron-transistor Device And Circuit Design

Summary

Author Biography

Table of Contents

Supplemental Materials