Integrated Circuit Failure Analysis A Guide

Fault analysis of highly-integrated semiconductor circuits has become an indispensable discipline in the optimization of product quality. Integrated Circuit Failure Analysis describes state-of-the-art procedures for exposing suspected failure sites in semiconductor devices. The author adopts a hands-on problem-oriented approach, founded on many years of practical experience, complemented by the explanation of basic theoretical principles. Features include: Advanced methods in device preparation and technical procedures for package inspection and semiconductor reliability. Illustration of chip isolation and step-by-step delayering of chips by wet chemical and modern plasma dry etching techniques. Particular analysis of bipolar and MOS circuits, although techniques are equally relevant to other semiconductors. Advice on the choice of suitable laboratory equipment. Numerous photographs and drawings providing guidance for checking results. Focusing on modern techniques, this practical text will enable both academic and industrial researchers and IC designers to expand the range of analytical and preparative methods at their disposal and to adapt to the needs of new technologies.

Friedrich Beck is the author of Integrated Circuit Failure Analysis: A Guide to Preparation Techniques, published by Wiley.

Series Foreword

xi

(2)

Preface

xiii

(2)

Acknowledgment and figure permissions

xv

(1)

Occupational safety information

xv

1 Purpose and importance of preparatory semiconductor analysis

1

(4)

1.1 Fault and failure

2

(1)

1.2 The concept of quality and reliability

3

(1)

References

3

(2)

2 Opening the package. Chip insulation

5

(26)

2.1 Opening metal packages

6

(1)

2.2 Opening ceramic packages

6

(3)

2.2.1 Removal of soldered metal covers

6

(2)

2.2.2 Removal of glued ceramic covers

8

(1)

2.2.3 Removal of soldered ceramic covers (glass solder)

8

(1)

2.3 Local opening of plastic packages

9

(10)

2.3.1 Local opening by manual chemical etching

10

(6)

2.3.2 Local opening by jet etching

16

(3)

2.3.3 Local opening by plasma etching

19

(1)

2.4 Complete removal of the package by dry chemical methods

19

(3)

2.5 Removal of covering layers above the chip

22

(2)

2.5.1 Removal of polyimides

23

(1)

2.5.2 Removal of silicones

24

(1)

2.5.3 Aftertreatment

24

(1)

2.6 Mechanical forcing open of the package

24

(2)

2.7 Removal of the chip from the carrier island

26

(2)

2.7.1 Removal of alloyed chips

26

(2)

2.7.2 Release of glued chips

28

(1)

References

28

(3)

3 Wet chemical etching procedures for removing layers of the chip structure

31

(26)

3.1 Removal of silicon nitride

32

(1)

3.2 Silicon oxide. Formation and etching

32

(7)

3.2.1 Formation and properties of silicon oxides

33

(2)

3.2.2 Etching of silicon oxide

35

(4)

3.3 Removal of aluminium

39

(1)

3.4 Removal of other metals

40

(4)

3.5 Removal of complex layers

44

(2)

3.6 Etching of silicon

46

(2)

3.6.1 Acid etching

46

(1)

3.6.2 Alkali etching

47

(1)

3.6.3 Etching by sequestering

48

(1)

3.7 Defect detection, structural representation

48

(2)

3.7.1 Defect detection in passivation and dielectrics

48

(1)

3.7.2 Grain-boundary etching on aluminium

49

(1)

3.7.3 Grain-boundary etching on polysilicon

49

(1)

3.8 Cleaning the chip surface

50

(3)

3.8.1 Removal of surface impurities

50

(3)

3.8.2 Cleaning of chips before crystallographic etching

53

(1)

References

53

(4)

4 Crystallographic etching in the silicon

57

(22)

4.1 Reaction modes and classification of the etching solutions

57

(1)

4.2 Structural etchants

58

(11)

4.3 Doping etchants

69

(7)

4.3.1 Etching mechanisms

69

(2)

4.3.2 Etching solutions with preferred etch attack on p-doped regions

71

(3)

4.3.3 Etching solutions with preferred attack on n-doped regions

74

(2)

References

76

(3)

5 Dry etching in the plasma

79

(40)

5.1 Importance of dry etching for fault analysis

79

(1)

5.2 Principle and features of dry etching procedures

80

(2)

5.3 Structure of etching apparatus. Conditions in the chamber

82

(5)

5.3.1 Principle of plasma etching

82

(1)

5.3.2 The tunnel or barrel reactor

82

(1)

5.3.3 The plate reactor, structure, potentials, currents

83

(4)

5.4 Etching modes: isotropic and anisotropic etching

87

(3)

5.4.1 Isotropic etching in the `plasma mode' (chemical etching)

87

(1)

5.4.2 Anisotropic etching with reactive ions (RIE mode, physical chemical etching), sidewall protection

88

(1)

5.4.3 Physical and mathematical relationships

89

(1)

5.5 Etching gases and how they react

90

(5)

5.5.1 Preferred etching gases for preparatory component analysis

90

(2)

5.5.2 Formation of reactive particles in the plasma and how they act

92

(2)

5.5.3 Polymer layers, residues

94

(1)

5.6 Effect of the etching parameters on the etching mode, etch rate and selectivity

95

(3)

5.6.1 Etching gases

95

(1)

5.6.2 Gas pressure

96

(1)

5.6.3 Gas flow

96

(1)

5.6.4 HF power, frequency and bias voltage

97

(1)

5.6.5 Temperature

97

(1)

5.7 Special procedures, new techniques

98

(1)

5.8 Radiation damage due to particles and electric fields

98

(1)

5.9 End-point detection

99

(4)

5.9.1 Importance of automatic end-point detection

99

(1)

5.9.2 Laser interferometry

100

(2)

5.9.3 Determination of layer thickness

102

(1)

5.10 Advice for plasma etching in the preparatory analysis

103

(10)

5.10.1 Overview

103

(1)

5.10.2 Choice of the etching procedure, avoidance of spacers

104

(2)

5.10.3 Handling the samples

106

(1)

5.10.4 Examples of `standard processes'

107

(6)

References

113

(4)

Conversion table for units of pressure

117

(2)

6 Microsectioning technology, metallography

119

(38)

6.1 Purpose and importance of metallographic preparations

119

(1)

6.2 Choice of the microsectioning direction

120

(2)

6.2.1 The perpendicular microsection

120

(1)

6.2.2 Oblique microsection

121

(1)

6.2.3 Angular microsection

122

(1)

6.3 Cutting large objects to size with the diamond saw

122

(2)

6.4 Breaking of chips and wafers. Production of deliberate crystallographic breaks

124

(4)

6.4.1 Manual procedures

124

(1)

6.4.2 Semi-automatic procedure with scoring and breaking device

125

(2)

6.4.3 Scoring on the HR 100 automatic scoring device

127

(1)

6.4.4 Precise scoring and separation with the laser. Fully automatic procedure

127

(1)

6.4.5 Cleaning after the breaking

127

(1)

6.5 The encapsulated microsection

128

(5)

6.5.1 Production of the moulds

128

(2)

6.5.2 Fixing and pouring in of the object

130

(1)

6.5.3 Coarse grinding, fine grinding to the target

131

(2)

6.6 The stand-alone microsection

133

(6)

6.6.1 Grinding and polishing equipment

134

(1)

6.6.2 Grinding block and object holder

135

(1)

6.6.3 Alignment of the object and fixing in the object holder

136

(1)

6.6.4 Coarse grinding and approach to the target position

137

(1)

6.6.5 Fine grinding to the target point (polishing)

137

(1)

6.6.6 Shaping of used polishing disks

138

(1)

6.7 The surface-parallel planar microsection

139

(3)

6.7.1 Structure of a planar section holder

140

(2)

6.8 Structuring of cross-sections and breaks

142

(13)

6.8.1 On structuring in general

142

(1)

6.8.2 Structuring procedures for silicon

143

(6)

6.8.3 Structuring of technology layers

149

(3)

6.8.4 Advice on method of working

152

(3)

References

155

(2)

7 Outlook

157

(2)

Appendix 1: Advice on health and safety at work

159

(6)

Identification of dangers, safety advice

160

(1)

Mandatory identification

160

(1)

Safety symbols

160

(1)

Practical information for handling acids, lyes, salts, solvents

161

(1)

Acids

161

(1)

Lyes and substances with an alkaline effect

161

(1)

Salt solutions

162

(1)

Hydrogen peroxide

162

(1)

Solvents

162

(3)

Appendix 2: List of manufacturers and suppliers

165

(4)

Index

169

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Integrated Circuit Failure Analysis A Guide to Preparation Techniques

Summary

Author Biography

Table of Contents

Supplemental Materials