Introduction to Pci Express

, by Wilen, Adam H.; Schade, Justin P.; Thornburg, Ron

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ISBN: 9780970284693 | 0970284691
Cover: Paperback
Copyright: 4/1/2003

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This book offers an introduction to the new I/O technology, PCI Express*, designed to allow increasing levels of computer system performance. The book details how PCI Express technology allows designers to overcome the practical performance limits of existing multi-drop, parallel bus technology. It explains how to increase performance and add new capabilities for a broad range of computing and communications platforms. Relevant technical considerations are presented that both hardware and software developers need to comprehend in order to employ PCI Express technology in next generation systems.

Acknowledgements	p. xi
Introduction	p. 1
A Quick Overview	p. 2
Why Develop a New I/O Technology?	p. 4
Who Should Read This Book	p. 6
System Integrators	p. 6
Hardware Developers	p. 6
Software Developers	p. 6
Product Marketing Engineers	p. 7
Application Engineers	p. 7
The Organization of This Book	p. 7
Beyond PCI	p. 7
The Technology	p. 8
Adopting PCI Express	p. 9
The PCI Legacy, Successes, and Challenges	p. 11
The Introduction of PCI	p. 11
PCI Successes	p. 13
Industry Acceptance	p. 14
Defined Specifications	p. 15
Processor Architecture Independence	p. 16
Full Bus Mastering	p. 18
Plug and Play Operation	p. 18
High Performance Low Cost Implementation	p. 19
PCI Challenges	p. 19
Bandwidth Limitations	p. 19
Host Pin Limitations	p. 21
Inability to Support Real-Time (Isochronous) Data Transfers	p. 23
Inability to Address Future I/O Requirements	p. 24
PCI Moving Forward	p. 25
Goals and Requirements	p. 27
Scalability, Stability, and Performance	p. 27
Stability Requirement: Stability for the Next Decade	p. 28
Scalability Requirement: Growth Options for the Future	p. 29
Performance Requirement: Pin and Link Efficiency	p. 31
Market Segment Support	p. 39
Market Segment Requirement: Mobile	p. 39
Market Segment Requirement: Desktop	p. 40
Market Segment Requirement: Servers	p. 41
Market Segment Requirement: Communications	p. 41
System-Level Cost Parity	p. 42
Cost Requirement: Ability to Use Common Printed Circuit Board Fabrication Technology	p. 42
Cost Requirement: Common Connector Manufacturing Technology	p. 43
Cost Requirement: Routing in Four-Layer Motherboards	p. 43
Cost Requirement: Usability on Multiple Silicon Process Technology	p. 44
I/O Simplification	p. 45
Simplification Requirement: I/O Consolidation	p. 46
Backward Compatibility	p. 49
Compatibility Requirement: Legacy Operating System Support	p. 49
Compatibility Requirement: Existing System Form Factor Support	p. 50
Compatibility Requirement: Allowing Coexistence During Transition	p. 50
PCI Express Applications	p. 51
Benefits of PCI Express	p. 51
High Performance	p. 52
I/O Simplification	p. 53
Layered Architecture	p. 54
Next Generation Multimedia	p. 55
Ease of Use	p. 56
Evolutionary Applications	p. 58
PCI Express for Computing Graphics Applications	p. 59
PCI Express for Gigabit Ethernet	p. 62
PCI Express as a High-Speed Chip-to-chip Interconnect	p. 65
Revolutionary Applications	p. 72
Multimedia and Isochronous Applications	p. 72
PCI Express Module Applications	p. 73
Communications Applications and Advanced Switching	p. 76
PCI Express Architecture Overview	p. 79
System Level Overview	p. 79
Links and Lanes	p. 80
Device Types	p. 83
PCI Express Transactions	p. 85
Transaction Types	p. 85
Build Layers	p. 86
Packet Formation	p. 87
The Big Picture	p. 89
Transaction Layer	p. 90
Data Link Layer	p. 92
Physical Layer	p. 94
Transaction Layer Architecture	p. 97
Transaction Layer Overview	p. 97
Transaction Layer Packets	p. 98
TLP Headers	p. 100
Memory Request Headers	p. 103
I/O Request Headers	p. 107
Configuration Request Headers	p. 108
Message Headers	p. 109
Completion Packet/Header	p. 115
TLP Data Payload	p. 117
TLP Digest	p. 119
TLP Handling	p. 120
Request Handling	p. 121
Completion Handling	p. 122
Data Link Layer Architecture	p. 123
Data Link Layer Overview	p. 123
Building on the TLP	p. 125
Sequence Number	p. 125
LCRC	p. 128
Retries	p. 128
Data Link Layer Packets (DLLPs)	p. 131
Ack and Nak DLLPs	p. 132
Flow Control DLLPs	p. 135
Power Management DLLPs	p. 136
Processing a DLLP	p. 136
Data Link Layer Control	p. 138
Physical Layer Architecture	p. 141
Physical Layer Organization	p. 141
Logical Sub-Block	p. 143
Electrical Sub-Block	p. 151
Link and Lane Training	p. 156
Surprise Insertion/Removal	p. 172
Surprise Insertion	p. 172
Surprise Removal	p. 173
Power Management Capabilities	p. 173
LOs Active Power Management State	p. 173
L1 Active Power Management State	p. 174
Flow Control	p. 175
Transaction Ordering	p. 175
Flow Control	p. 178
Flow Control Rules	p. 179
Flow Control Credits	p. 182
Virtual Channels and Traffic Classes	p. 186
Traffic Class to Virtual Channel Mapping	p. 188
Virtual Channel Initialization	p. 190
Isochronous Support	p. 197
PCI Express Software Overview	p. 201
Software Initialization and Configuration	p. 201
Refresher on PCI Configuration	p. 202
Configuration Mechanisms	p. 204
Error Reporting	p. 206
Error Classification	p. 207
Error Signaling	p. 209
Advanced Error Capabilities Configuration	p. 210
Error Logging	p. 212
Software Particulars for Key PCI Express Features	p. 214
PCI Express Power Management	p. 214
PCI Express Hot Plug	p. 215
PCI Express Differentiated Traffic Support	p. 218
Virtual Channel Capabilities Configuration	p. 219
Available Arbitration Mechanisms	p. 220
The Virtual Channel Arbitration Table and the Port Arbitration Table	p. 222
Power Management	p. 227
Building on PCI Power Management	p. 227
PCI Power Management Software Base Operations	p. 229
PCI Bus States versus PCI Express Link States	p. 232
PCI Express Link State L0 and PCI Bus State B0	p. 235
PCI Express Link State L0s	p. 235
PCI Express Link States L1, L2, and PCI Bus State B2	p. 236
PCI Express Link State L3 and PCI Bus State B3	p. 237
PCI Express Link State L2/L3 Ready	p. 237
PCI Express Link Recovery State	p. 237
PCI Express Link Training States	p. 238
PCI Express Active State Power Management ASPM	p. 240
Software Requirements for PCI Express Active State Power Management	p. 241
L0s Active State Power Management	p. 244
L1 Active State Power Management	p. 245
Power Management Messages and Packets	p. 245
PCI Express Implementation	p. 249
System Partitioning	p. 249
Desktop Partitioning	p. 251
Mobile Partitioning	p. 254
Server Partitioning	p. 256
Impact on System Architecture	p. 258
Form Factors	p. 259
Connectors	p. 261
Routing Implications	p. 265
PCI Express Timetable	p. 273
Anticipated Schedule	p. 273
Application Roll Out	p. 273
Factors Affecting Adoption and Schedule	p. 274
Profile of an Early Adopter	p. 278
Challenges of Early Adoption	p. 280
Benefits of Early Adoption	p. 281
Tools for Early Adopters	p. 282
Profile of a Later Adopter	p. 284
Challenges of Late Adoption	p. 284
Benefits and Tools for Later Adopters	p. 286
PCI Express Product Definition and Planning	p. 287
PC Graphics Components as an Example	p. 287
Market Assessment	p. 288
Design Tradeoffs and Key Decisions	p. 288
Motherboard Vendors as an Example	p. 298
Market Assessment versus Cost	p. 298
Design Tradeoffs and Key Decisions	p. 301
Conclusion	p. 302
PCI Express Compliance & Interoperability	p. 305
Compliance and Interoperability Terminology	p. 306
Compliance Development Process	p. 307
Compliance Testing	p. 308
Platform Components	p. 308
Add-in Card Components	p. 309
Interoperability Testing	p. 310
Plugfests	p. 311
Useful References	p. 311
Glossary	p. 313
Index	p. 319
Table of Contents provided by Ingram. All Rights Reserved.

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