Ixp1200 Programming

Guide shows software engineers how to program the microengines of Intel's IXP12xx network processors. Provides an explanation of the hardware and development environment. Softcover. CD-ROM included.

Foreword

xi

Acknowledgements

xiii

So you got your first IXP12xx, now what?

1

(6)

Is this book for you?

2

(1)

It isn't that scary

3

(1)

A guide to the rest of the book

4

(1)

Conventions

5

(2)

The IXP12xx Programming Environment

7

(30)

Programmable Processing Units

8

(7)

StrongARM Core

9

(1)

Microengines

9

(6)

Other Functional Units

15

(9)

Memory Interfaces

15

(2)

Scratchpad

17

(1)

SRAM

17

(1)

SDRAM

18

(3)

The FBI

21

(3)

The Ready-bus Sequencer

24

(2)

The IXP12xx Family

26

(1)

A Day in the Life of a Packet

27

(3)

The Software

30

(5)

Programming Languages

30

(2)

Libraries

32

(1)

Development Environments

33

(1)

Programming Frameworks

33

(2)

Summary

35

(1)

Further Reading

36

(1)

``Hello World'' for the Microengines

37

(18)

Installing the Tools

37

(1)

Setting Up the Workspace

38

(3)

Writing the Program

41

(6)

Compiling a Simple Source File

41

(4)

Adding Code to the Source File

45

(2)

Examining the Microcode

47

(3)

Simulating the Program

50

(4)

Summary

54

(1)

Microblock Design Philosophy

55

(6)

The Philosophy

55

(5)

Performance

56

(2)

Modularity

58

(2)

Exceptions

60

(1)

Summary

60

(1)

Receiving and Processing Basics

61

(38)

Turning Packets into Mpackets

62

(2)

Turning Mpackets Back into Packets

64

(27)

Receiving One Mpacket

67

(9)

Moving Mpackets into Buffers: The Receive_Packet Microblock

76

(15)

Putting It All Together: Counting Packets

91

(6)

Debugging and Inspecting the Results

93

(4)

Summary

97

(2)

Intra-microengine Programming Concepts

99

(28)

Determining the Single-threaded Performance

100

(3)

The Overhead of Multithreading

103

(7)

The Non-preemptive Thread Arbiter

105

(5)

Intra-microengine Communication: Shared Variables

110

(3)

Multithreaded Packet Counting Code

113

(11)

Inside the Performance Numbers

120

(4)

Is the Code Too Fast?

124

(2)

Summary

126

(1)

Inter-microengine Programming Concepts

127

(44)

Intra- vs Inter-microengine Programming

128

(1)

Using Atomic Bit Operations

129

(14)

Performance Analysis with Atomic Bit-Test-and-Set

138

(5)

Using SRAM CAM Locks

143

(10)

Performance Analysis with SRAM CAM Locks

147

(2)

Properties of SRAM CAM Locks

149

(4)

Using Inter-thread Signals

153

(8)

Performance Analysis with Inter-thread Signals

159

(2)

An Overview of Microengine and Core Communication

161

(8)

The Core Memory Map for SRAM

162

(2)

Core Atomic Bit Operations

164

(2)

Core SRAM CAM Lock and Unlock

166

(2)

Core SRAM LIFO Push and Pop Access

168

(1)

Core Inter-thread Signals

169

(1)

Summary

169

(2)

Fast Data Structure Processing

171

(24)

Architectural Considerations

171

(6)

Latency Hiding

172

(2)

Parallelism

174

(1)

Hashing

174

(3)

An Example: Ethernet Bridging

177

(11)

Algorithm

177

(1)

Hash Unit

178

(4)

Parallelism

182

(3)

Latency Hiding

185

(3)

Another Example: Queuing

188

(6)

Parallelism: Two Different Data Structures

189

(4)

Latency Hiding

193

(1)

Summary

194

(1)

Transmitting Data

195

(22)

Transmit State Machine

195

(11)

A Transmit Design and Implementation

206

(6)

The Design

206

(2)

The Code

208

(4)

Multi-port Transmit Design

212

(4)

Summary

216

(1)

Advanced Programming Topics

217

(32)

Receiving Packets from Fast-port MAC Devices

218

(21)

Speculative Receive-requests

220

(2)

Detecting Cancelled Speculative Receive-requests

222

(1)

Maintaining Ordering When Using Speculative Receive-requests

223

(3)

Putting It All Together: Complete Fast Port Receive Code

226

(13)

Transmitting Packets on Multiple Ports with Different Speeds

239

(4)

Dedicating Microengines to Ports

239

(3)

Dedicating Microengines to Tasks

242

(1)

Which Design is Better?

243

(1)

Programming the Ready-bus Sequencer

243

(3)

An Overview of the CRC Feature of the IXP1240 and IXP1250

246

(2)

Summary

248

(1)

Writing microACEs

249

(28)

What is a microACE?

249

(7)

Dispatch Loops

253

(2)

Resource Manager

255

(1)

Why Use the IXA SDK?

256

(1)

Building a microACE

257

(17)

Writing the IDL Interface

257

(3)

Writing Initialization and Shutdown Code

260

(5)

Implementing the IDL Interface

265

(2)

Writing Microblock Code

267

(2)

Writing Code to Handle Packets Sent from the Microblock to the Core Component

269

(3)

Writing Code to Handle Packets Sent from Other Core ACEs to the Core Component

272

(2)

Summary

274

(1)

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