Logic and Computer Design Fundamentals and Xilinx 4.2 Package

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ISBN: 9780131794733 | 0131794736
Cover: Paperback
Copyright: 1/1/2001

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Summary

Supplemental Materials

THE CONTENTS OF THIS PACKAGE INCLUDES:

0130314862 > LOGIC&CMPTR DESGN UPDATD
0130451908 > XILINX STU ED4.2I VALUPK

Preface

Digital Computers and Information

(24)

Digital Computers

(5)

Information Representation

(1)

Computer Structure

(1)

More on the Generic Computer

(2)

Number Systems

(5)

Binary Numbers

(1)

Octal and Hexadecimal Numbers

(2)

Number Ranges

(1)

Arithmetic Operations

(4)

Conversion from Decimal to Other Bases

(2)

Decimal Codes

(3)

BCD Addition

(1)

Alphanumeric Codes

(3)

ASCII Character Code

(2)

Parity Bit

(1)

Chapter Summary

(4)

References

(1)

Problems

(3)

Combinational Logic Circuits

(64)

Binary Logic and Gates

(4)

Binary Logic

(2)

Logic Gates

(1)

Boolean Algebra

(8)

Basic Identities of Boolean Algebra

(2)

Algebraic Manipulation

(3)

Complement of a Function

(1)

Standard Forms

(6)

Minterms and Maxterms

(4)

Sum of Products

(1)

Product of Sums

(1)

Map Simplification

(10)

Two-Variable Map

(1)

Three-Variable Map

(5)

Four-Variable Map

(3)

Map Manipulation

(7)

Essential Prime Implicants

(2)

Nonessential Prime Implicants

(1)

Product-of Sums Simplification

(2)

Don't-Care Conditions

(2)

NAND and NOR Gates

(9)

NAND Circuits

(1)

Two-Level Implementation

(2)

Multilevel NAND Circuits

(2)

NOR Circuits

(2)

Exclusive-OR Gates

(5)

Odd Function

(1)

Parity Generation and Checking

(2)

Integrated Circuits

(6)

Levels of Integration

(1)

Digital Logic Families

(3)

Positive and Negative Logic

(2)

Transmission Gates

(1)

Chapter Summary

(9)

References

(1)

Problems

(8)

Combinational Logic Design

(92)

Combinational Circuits

(1)

Design Topics

(8)

Design Hierarchy

(3)

Top-Down Design

(1)

Computer-Aided Design

(1)

Hardware Description Languages

(2)

Logic Synthesis

(1)

Analysis Procedure

100

(5)

Derivation of Boolean Functions

101

(1)

Derivation of the Truth Table

102

(1)

Logic Simulation

103

(2)

Design Procedure

105

(6)

Code Converters

107

(4)

Decoders

111

(5)

Decoder Expansion

113

(1)

Combinational Circuit Implementation

114

(2)

Encoders

116

(3)

Priority Encoder

117

(2)

Multiplexers

119

(6)

Combinational Circuit Implementation

122

(2)

Demultiplexer

124

(1)

Binary Adders

125

(7)

Half Adder

125

(1)

Full Adder

126

(1)

Binary Ripple Carry Adder

127

(2)

Carry Lookahead Adder

129

(3)

Binary Subtraction

132

(5)

Complements

134

(1)

Subtraction with Complements

135

(2)

Binary Adder-Subtractors

137

(7)

Signed Binary Numbers

138

(2)

Signed Binary Addition and Subtraction

140

(2)

Overflow

142

(2)

Binary Multipliers

144

(1)

Decimal Arithmetic

145

(3)

Use of Complements in Decimal

147

(1)

HDL Representations - VHDL

148

(11)

Structural Description

150

(3)

Dataflow Description

153

(2)

Hierarchical Description

155

(2)

Behavioral Description

157

(2)

HDL Representations - Verilog

159

(8)

Structural Description

160

(1)

Dataflow Description

161

(4)

Hierarchical Description

165

(1)

Behavioral Description

165

(2)

Chapter Summary

167

(16)

References

168

(1)

Problems

168

(15)

Sequential Circuits

183

(66)

Sequential Circuit Definitions

184

(2)

Latches

186

(5)

SR and S R Latches

187

(3)

D Latch

190

(1)

Flip-Flops

191

(10)

Master-Slave Flip-Flop

192

(3)

Edge-Triggered Flip-Flop

195

(2)

Standard Graphics Symbols

197

(2)

Characteristic Tables

199

(1)

Direct Inputs

200

(1)

Sequential Circuit Analysis

201

(7)

Input Equations

201

(1)

State Table

202

(4)

Analysis with JK Flip-Flops

206

(1)

State Diagram

206

(2)

Sequential Circuit Design

208

(6)

Design Procedure

208

(1)

Finding State Diagrams and State Tables

209

(5)

Designing with D Flip-Flops

214

(4)

Designing with Unused States

215

(3)

Designing with JK Flip-Flops

218

(6)

Flip-Flop Excitation Tables

218

(1)

Design Procedure

219

(5)

HDL Representation for Sequential Circuits - VHDL

224

(8)

HDL Representation for Sequential Circuits - Verilog

232

(7)

References

239

(10)

Problems

240

(9)

Registers and Counters

249

(36)

Definition of Register and Counter

249

(1)

Registers

250

(3)

251

(2)

Shift Registers

253

(8)

Serial Transfer

254

(2)

Serial Addition

256

(2)

Shift Register with Parallel Load

258

(2)

Bidirectional Shift Register

260

(1)

Ripple Counter

261

(2)

Synchronous Binary Counters

263

(10)

Design of Binary Counters

264

(3)

Counter with D Flip-Flops

267

(1)

Serial and Parallel Counters

268

(1)

Up-Down Binary Counter

269

(1)

Binary Counter with Parallel Load

270

(3)

Other Counters

273

(3)

BCD Counter

273

(1)

Arbitrary Count Sequence

274

(2)

HDL Representation for Shift Registers and Counters

276

(2)

HDL Representation for Shift Registers and Counters

278

(1)

Chapter Summary

279

(6)

References

280

(1)

Problems

280

(5)

Memory and Programmable Logic Devices

285

(54)

Memory and Programmable Logic Device

285

(2)

Definitions

286

(1)

Random-access Memory

287

(5)

Write and Read Operations

289

(1)

Timing Waveforms

290

(2)

Properties of Memory

292

(1)

RAM Integrated Circuits

292

(15)

Three-State Buffers

296

(1)

Coincident Selection

297

(4)

Dynamic RAM ICs

301

(6)

Array of RAM ICs

307

(3)

Arrays of Dynamic RAM ICs

310

(1)

Programmable Logic Technologies

310

(2)

Read-only Memory

312

(5)

Combinational Circuit Implementation

315

(2)

Programmable Logic Array

317

(4)

Programmable Array Logic Devices

321

(5)

VLSI Programmable Logic Devices

326

(7)

Altera MAX 7000 CPLDs

326

(2)

Xilinx XC4000 Structure

328

(2)

Xilinx Interconnections

330

(1)

Xilinx Logic

331

(2)

Chapter Summary

333

(6)

References

334

(1)

Problems

335

(4)

339

(52)

Datapaths and Operations

340

(1)

341

(4)

A Note For VHDL And Verilog Users Only

344

(1)

Microoperations

345

(5)

Arithmetic Microoperations

345

(2)

Logic Microoperations

347

(2)

Shift Microoperations

349

(1)

Multiplexer-based Transfer

350

(1)

Bus-based Transfer

351

(6)

Three-State Bus

353

(2)

Memory Transfer

355

(2)

Datapaths

357

(3)

The Arithmetic/Logic Unit

360

(6)

Arithmetic Circuit

360

(3)

Logic Circuit

363

(1)

Arithmetic/Logic Unit

364

(2)

The Shifter

366

(2)

Barrel Shifter

367

(1)

Datapath Representation

368

(2)

The Control Word

370

(6)

Pipelined Datapath

376

(6)

Execution of Pipeline Microoperations

381

(1)

Chapter Summary

382

(9)

References

383

(1)

Problems

383

(8)

Sequencing and Control

391

(76)

The Control Unit

392

(1)

Algorithmic State Machines

393

(4)

The ASM Chart

393

(3)

Timing Considerations

396

(1)

Design Example: Binary Multiplier

397

(5)

Binary Multiplier

397

(2)

Multiplier Datapath

399

(1)

ASM Chart for Multiplier

400

(2)

Hardwired Control

402

(8)

Sequence Register and Decoder

404

(2)

One Flip-Flop per State

406

(4)

HDL Representation of the Binary Multiplier - VHDL

410

(3)

HDL Representation of the Binary Multiplier - Verilog

413

(3)

Microprogrammed Control

416

(8)

Binary Multiplier Example

418

(6)

A Simple Computer Architecture

424

(5)

Instructions

424

(1)

Instruction Formats

425

(3)

Storage Resource Diagram

428

(1)

Single-Cycle Hardwired Control

429

(8)

Instruction Decoder

431

(2)

Sample Instructions and Program

433

(4)

Multiple-Cycle Microprogrammed Control

437

(13)

Microprogram Design

440

(7)

The Hardwired Alternative

447

(3)

Pipelined Control

450

(5)

Pipeline Programming and Performance

453

(2)

Chapter Summary

455

(12)

References

456

(1)

Problems

456

(11)

Instruction Set Architecture

467

(44)

Computer Architecture Concepts

467

(2)

Basic Computer Operation Cycle

468

(1)

469

(1)

Operand Addressing

469

(7)

Three-address Instructions

470

(1)

Two-address Instructions

471

(1)

One-address Instructions

471

(1)

Zero-address Instructions

472

(1)

Addressing Architectures

473

(3)

Addressing Modes

476

(6)

Implied Mode

477

(1)

Immediate Mode

477

(1)

477

(1)

Direct Addressing Mode

478

(2)

Indirect Addressing Mode

480

(1)

Relative Addressing Mode

480

(1)

Indexed Addressing Mode

481

(1)

Summary of Addressing Modes

482

(1)

Instruction Set Architectures

482

(2)

Data Transfer Instructions

484

(3)

Stack Instructions

484

(2)

Independent versus Memory-Mapped I/O

486

(1)

Data Manipulation Instructions

487

(4)

Arithmetic Instructions

487

(1)

Logical and Bit Manipulation Instructions

488

(2)

Shift Instructions

490

(1)

Floating-point Computations

491

(4)

Arithmetic Operations

492

(1)

Biased Exponent

493

(1)

Standard Operand Format

493

(2)

Program Control Instructions

495

(5)

Conditional Branch Instructions

497

(2)

Procedure Call and Return Instructions

499

(1)

Program Interrupt

500

(4)

Types of Interrupts

502

(1)

Processing External Interrupts

503

(1)

Chapter Summary

504

(7)

References

505

(1)

Problems

505

(6)

Central Processing Unit Designs

511

(64)

Two CPU Designs

511

(1)

The Complex Instruction Set Computer

512

(30)

Instruction Set Architecture

512

(5)

Datapath Organization

517

(6)

Microprogrammed Control Organization

523

(8)

Microprogram Structure

531

(2)

Microroutines

533

(9)

The Reduced Instruction Set Computer

542

(20)

Instruction Set Architecture

542

(3)

Addressing Modes

545

(1)

Datapath Organization

546

(3)

Control Organization

549

(2)

Data Hazards

551

(7)

Control Hazards

558

(4)

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Logic and Computer Design Fundamentals and Xilinx 4.2 Package

Summary

Table of Contents

Supplemental Materials