CMOS Front-End Materials and Process

In the future, because fundamental materials and process limits are being approached, continued transistor scaling will not be as straightforward. Future complementary metal-oxide semiconductor (MOS) transistors will require high-permittivity (high-k) gate dielectrics and metal gate electrodes, as well as low-resistance ultrashallow junctions, in order to meet the stringent specifications of the International Technology Roadmap for Semiconductors. Techniques to improve transconductance and drive current may also be required. Process integration issues must be solved, and reliability must be assured, before any new material or processing technique can be used in IC manufacture. A further complication is that the key challenges will differ according to application. This book reports research results from industry, government labs and academia covering a wide scope of front-end process issues for future CMOS technologies. Topics include: advanced materials and structures; high-k dielectrics; advanced gate stack materials; heterogeneous integration and strained Si technologies; ultrashallow junction technology; strained Si and source/drain technology; and laser annealing and silicide processes.

Preface	p. xi
Materials Research Society Symposium Proceedings	p. xii
Advanced Materials and Structures
Stacked Metal Layers as Gates for MOSFET Threshold Voltage Control	p. 3
Evolution of SOI MOSFETs: From Single Gate to Multiple Gates	p. 9
A Technique for Source/Drain Elevation Using Implantation Mediated Selective Etching	p. 21
Study Using Elements from Group IIA as Barriers for Dopant Penetration Into Gate Dielectrics and Getters for Metallic Ion Contamination	p. 27
Search for New High-k Dielectrics by Combinatorial Chemical Vapor Deposition	p. 33
High-k Dielectrics
Impact of Gate Process Technology on EOT of HfO[subscript 2] gate Dielectric	p. 41
High-k Materials for Advanced Gate Stack Dielectrics: A Comparison of ALCVD and MOCVD as Deposition Technologies	p. 47
Scalability of MOCVD-Deposited Hafnium Oxide	p. 59
Physical-Chemical Evolution of Hf-Aluminates Upon Thermal Treatments	p. 65
Advanced Gate Stack Materials
A New Parameter Predicating G[subscript m] for Ultra Thin Nitrided Gate Oxide	p. 73
Kinetics of Charge Generation During Formation of Hf and Zr Silicate Dielectrics	p. 79
Limiting Native Oxide Regrowth for High-k Gate Dielectrics	p. 85
Thin HfO[subscript 2] Films Deposited via Alternating Pulses of Hf(NO[subscript 3])[subscript 4] and HfCl[subscript 4]	p. 91
Atomic Layer Deposition of Hafnium Oxide Thin Films From Tetrakis(dimethylamino)Hafnium (TDMAH) and Ozone	p. 97
Evaluation of Tetrakis(diethylamino)Hafnium Precursor in the Formation of Hafnium Oxide Films Using Atomic Layer Deposition	p. 103
Flat-Band Voltage Study of Atomic-Layer-Deposited Aluminum-Oxide Subjected to Spike Thermal Annealing	p. 109
LS-MOCVD of BSTO Thin Films Using Novel Ba and Sr Precursors	p. 115
The Pr[subscript 2]O[subscript 3]/Si(001) Interface: A Mixed Si-Pr Oxide	p. 121
Low Temperature Si[subscript 0.85]Ge[subscript 0.15] Oxynitridation in Wet-Nitric Oxide Ambient	p. 127
Heterogeneous Integration and Strained Si Technologies
Relaxation of SiGe Films for the Fabrication of Strained Si Devices	p. 135
Free Standing Silicon as a Compliant Substrate for SiGe	p. 141
Relaxed SiGe Layers With High Ge Content by Compliant Substrates	p. 147
Hybrid Valence Bands in Strained-Layer Heterostructures Grown on Relaxed SiGe Virtual Substrates	p. 153
Ultra-Shallow Junction Technology
B Diffusion in Low Energy B/BF[subscript 2] Implants With Pre-Amorphization of Different Species	p. 161
Segregation and Diffusion of Sb Compared to As for Ultra-Shallow Implantation Into Silicon	p. 167
Atomistic Simulations of Effect of Coulombic Interactions on Carrier Fluctuations in Doped Silicon	p. 173
Dopant Diffusion Simulation in Thin-SOI	p. 179
Theory and Simulation of Dopant Diffusion in SiGe	p. 185
Strained Si and Source/Drain Technology
Short-Period (Si[subscript 14]/Si[subscript 0.75]Ge[subscript 0.25])[subscript 20] Superlattices for the Growth of High-Quality Si[subscript 0.75]Ge[subscript 0.25] Alloy Layers	p. 193
Physics-Based Diffusion Simulations for Preamorphized Ultra-Shallow Junctions	p. 199
Indium in Silicon: A Study on Diffusion and Electrical Activation	p. 205
Investigation and Modeling of Fluorine Co-Implantation Effects on Dopant Redistribution	p. 211
Diffusion of Boron in Germanium and Si[subscript 1-x]Ge[subscript x] (x [right than sign]50%) Alloys	p. 217
Boron Segregation and Out-Diffusion in Single-Crystal Si[subscript 1-y]C[subscript y]	p. 223
Process Optimization for Multiple-Pulses Laser Annealing for Boron Implanted Silicon with Germanium Pre-Amorphization	p. 229
Formation of NiSi-Silicided p[superscript +]n Shallow Junctions Using Implant Through Silicide and Low Temperature Furnace Annealing	p. 235
Laser Annealing and Silicide Processes
Ultra-Shallow Junction Formation by Excimer Laser Annealing of Ultra-Low Energy B Implanted in Si	p. 243
Experiment and Modelization Results on Laser Thermal Processing for Ultra-Shallow Junction Formation: Influence of Laser Pulse Duration	p. 255
A Comparison of Spike, Flash, SPER and Laser Annealing for 45 nm CMOS	p. 261
Silicides for 65 nm CMOS and Beyond	p. 267
Low Resistivity Nickel Germanosilicide Contacts to Ultra-Shallow Junctions Formed by the Selective Si[subscript 1-x]Ge[subscript x] Technology for Nanoscale CMOS	p. 279
NiSi Formation in the Ni(Ti)/SiO[subscript 2]/Si System	p. 285
Performance of Pt-Based Low Schottky Barrier Silicide Contacts on Weakly Doped Silicon	p. 291
Low Schottky Barrier on N-Type Si for N-Channel Schottky Source/Drain MOSFETs	p. 297
Author Index	p. 303
Subject Index	p. 307
Table of Contents provided by Ingram. All Rights Reserved.

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CMOS Front-End Materials and Process Technology

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