Silicon Nanoelectronics

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ISBN: 9780824726331 | 0824726332
Cover: Hardcover
Copyright: 6/27/2005

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Because the silicon process infrastructure is already in place and because of silicon's compatibility with current CMOS circuits, silicon nanodevices are positioned to become particularly important. Silicon Nanoelectronics examines recent developments of novel devices and materials that hold great promise for creating smaller and more powerful chips. Contributed by more than 20 leading researchers, the text offers extensive background information and considers issues such as quantum effects and ballistic transport and resonant tunneling in silicon nanotechnology. It also pays significant attention to the all-important silicon single electron transistors and the devices that utilize them.

Chapter 1 Physics of Silicon Nanodevices

(32)

David K. Ferry, Richard Akis, Matthew J. Gilbert, and Stephen M. Ramey

1.1 Introduction

(1)

1.2. Small MOSFETs

(6)

1.2.1 The Simple One-Dimensional Theory

(1)

1.2.2 Ballistic Transport in the MOSFET

(4)

1.3 Granularity

(2)

1.4 Quantum Behavior in the Device

(13)

1.4.1 The Effective Potential

(6)

1.4.1.1 Effective Carrier Wave Packet

(2)

1.4.1.2 Statistical Considerations

(3)

1.4.2. Quantum Simulations

(17)

1.4.2.1 The Device Structure

(1)

1.4.2.2 The Wave Function and Technique

(4)

1.4.2.3 Results

(2)

1.5 Quantum Dot Single-Electron Devices

(1)

1.6 Many-Body Interactions

(3)

1.7 Acknowledgments

(1)

References

(7)

Chapter 2 Practical CMOS Scaling

(32)

David J. Frank

2.1 Introduction

(1)

2.2 CMOS Technology Overview

(3)

2.2.1 Current CMOS Device Technology

(2)

2.2.2 International Technology Roadmap for Semiconductors (ITRS) Projections

(1)

2.3 Scaling Principles

(4)

2.2.1 General Scaling

(1)

2.3.2 Characteristic Scale Length

(2)

2.4 Exploratory Technology

(8)

2.4.1 New Materials

(1)

2.4.2 Fully Depleted SOI

(1)

2.4.3 Double-Gate and Multiple-Gate FET Structures

(5)

2.5 Limits to Scaling

(6)

2.5.1 Quantum Mechanics

(2)

2.5.2 Atomistic Effects

(3)

2.5.3 Thermodynamic Effects

(1)

2.5.4 Practical Considerations

(1)

2.6 Power-Constrained Scaling Limits

(4)

2.7 Summary

(1)

Acknowledgments

(1)

References

(7)

Chapter 3 The Scaling Limit of MOSFETs due to Direct Source-Drain Tunneling

(24)

Hisao Kawaura

3.1 Introduction

(3)

3.2 EJ-MOSFETs

(7)

3.2.1 Concept of EJ-MOSFETs

(2)

3.2.2 Fabrication of the Device Structure

(2)

3.2.3 Basic Operation

(3)

3.3 Direct Source-Drain Tunneling

(8)

3.3.1 Detection of the Tunneling Current

(3)

3.3.2 Numerical Study of the Tunneling Current

(5)

3.4 The Scaling Limit of MOSFETs

(3)

3.4.1 Estimation of Direct Source-Drain Tunneling in MOSFETs

(2)

3.4.2 Future Trends in Post-6-nm MOSFETs

(1)

3.5 Conclusion

(1)

Acknowledgments

(1)

References

(3)

Chapter 4 Quantum Effects in Silicon Nanodevices

(16)

Toshiro Hiramoto

4.1 Introduction

(1)

4.2 Quantum Effects in MOSFETs

(3)

4.2.1 Band Structures of Silicon

(1)

4.2.2 Surface Quantization

(2)

4.2.3 Carrier Confinement in Thin SOI MOS Structures

(1)

4.2.4 Mobility of Confined Carriers

(1)

4.3 Influences of Quantum Effects in MOSFETs

(2)

4.3.1 Threshold Voltage Increase in Bulk MOSFETs

(1)

4.3.2 Threshold Voltage Increase in FD-SOI MOSFETs

(1)

4.3.3 Mobility in Ultrathin FD-SOI MOSFETs

(1)

4.4 Quantum Effects in Ultranarrow Channel MOSFETs

(7)

4.4.1 Advantage of Quantum Effects in Ultranarrow Channel MOSFETs

(1)

4.4.2 Threshold Voltage Increase in n-Type Narrow Channel MOSFETs

(2)

4.4.3 Threshold Voltage Increase in n-Type and p-Type Narrow Channel MOSFETs

(2)

4.4.4 Threshold Voltage Adjustment Using Quantum Effects

(1)

4.4.5 Mobility Enhancement due to Quantum Effects

100

(2)

4.5 Summary

102

(1)

References

103

(2)

Chapter 5 Ballistic Transport in Silicon Nanostructures

105

(28)

Hiroshi Mizuta, Katsuhiko Nishiguchi and Shunri Oda

5.1 Introduction

105

(1)

5.2 Ballistic Transport in Quantum Point Contacts

106

(7)

5.3 Ballistic Transport in Ultra-Short Channel Vertical Silicon Transistors

113

(15)

5.3.1 Fabrication of Nanoscale Vertical FETs

113

(4)

5.3.2 Conductance Quantization in Nanoscale Vertical FETs

117

(4)

5.3.3 Characteristics under a Magnetic Field

121

(4)

5.3.4 Effects of Cross-Sectional Channel Geometries

125

(3)

5.4 Summary and Future Subjects

128

(1)

References

129

(4)

Chapter 6 Resonant Tunneling in Si Nanodevices

133

(22)

Michiharu Tabe, Hiroya Ikeda, and Yasuhiko Ishikawa

6.1 Introduction

133

(6)

6.1.1 Outline of Resonant Tunneling

133

(1)

6.1.1.1 Early Work on Resonant Tunneling

133

(1)

6.1.1.2 Resonant Tunneling in Si-Based Materials - Si/SiGe and Si/SiO2

134

(1)

6.1.2 Quantum Confinement Effect in a Thin Si Layer

134

(2)

6.1.3 Double-Barrier Structures of SiO2/Si/SiO2 Formed by Anisotropic Etching

136

(3)

6.2 Resonant Tunneling in SiO2/Si/SiO2

139

(9)

6.2.1 Fabrication of an RTD

139

(2)

6.2.2 Resonant Tunneling in the Low Voltage Region

141

(2)

6.2.3 Hot-Electron Storage in the High-Voltage Region

143

(4)

6.2.4 Switching of Tunnel-Modes: Comparison with a Single Barrier

147

(1)

6.3 Zero-Dimensional Resonant Tunneling

148

(4)

6.3.1 Coexistence of Coulomb Blockade and Resonant Tunneling

148

(1)

6.3.2 Fabrication of a SiO2/Si-Dots/SiO2 Structure

149

(2)

6.3.3 I-V Characteristics of an SiO2/Si-Dots/SiO2 Tunnel Diode

151

(1)

Acknowledgment

152

(1)

References

152

(3)

Chapter 7 Silicon Single-Electron Transistor and Memory

155

(40)

L. Jay Guo

7.1 Introduction

155

(3)

7.1.1 Quantum Dot Transistor

156

(2)

7.2 Theoretical Background

158

(7)

7.2.1 Energy of the Quantum Dot System

159

(2)

7.2.2 Conductance Oscillation and Potential Fluctuation

161

(1)

7.2.3 Transport under Finite Temperature and Finite Bias

162

(3)

7.3 Device Structure and Fabrication

165

(1)

7.4 Experimental Results and Analysis

166

(7)

7.4.1 Single-Electron Quantum-Dot Transistor

167

(1)

7.4.2 Single-Hole Quantum-Dot Transistor

168

(1)

7.4.3 Transport Characteristics under Finite Bias

169

(3)

7.4.4 Transport Through Excited States

172

(1)

7.5 Artificial Atom

173

(1)

7.6 Single Charge Trapping

174

(2)

7.7 Introduction to Memory Devices

176

(1)

7.8 Floating Gate Scheme

177

(2)

7.9 Single-Electron MOS memory (SEMM)

179

(8)

7.9.1 Structure of SEMM

179

(1)

7.9.2 Fabrication Procedure

180

(1)

7.9.3 Experimental Observations

181

(2)

7.9.4 Analysis

183

(3)

7.9.5 Effects of Trap States

186

(1)

7.10 Effect of Thicker Tunnel Oxide

187

(3)

7.11 Discussion

190

(1)

References

191

(4)

Chapter 8 Silicon Memories Using Quantum and Single-Electron Effects

195

(28)

Sandip Tiwari

8.1 Introduction

195

(1)

8.2 Single-Electron Effect

196

(3)

8.3 Single-Electron Transistors and Their Memories

199

(5)

8.3.2 Memories by Scaling Floating Gates of Flash Structures

200

(4)

8.4 Modeling of Transport: Tunneling

204

(4)

8.4.1 Tunneling in Oxide

204

(1)

8.4.2 Quantum Kinetic Equation

205

(2)

8.4.3 Carrier Statistics and Charge Fluctuations

207

(1)

8.5 Experimental Behavior of Memories

208

(9)

8.5.1 Percolation Effects

212

(1)

8.5.2 Limitations in Use of Field Effect

212

(1)

8.5.3 Confinement and Random Effects in Semiconductors

213

(1)

8.5.4 Variances due to Dimensions

213

(2)

8.5.5 Limits due to Tunneling

215

(8)

8.5.5.1 Tunneling in Oxide

215

(1)

8.5.5.2 Tunneling in Silicon

215

(2)

8.6 Can We Avoid Use of Collective Phenomena?

217

(2)

8.7 Summary

219

(1)

References

220

(3)

Chapter 9 SESO Memory Devices

223

(20)

Kazuo Yano

9.1 Introduction

223

(2)

9.1.1 How Nanotechnologies Solve Real Problems

223

(1)

9.1.2 New Direction of Electronics

223

(2)

9.2 Conventional Memory Technologies

225

(2)

9.2.1 Classification of Conventional Memories

225

(1)

9.2.2 Origin of DRAM Power Consumption

226

(1)

9.3 Bandgap Enlargement in Nanosilicon

227

(3)

9.4 SESO Transistor

230

(2)

9.4.1 History: Single-Electron Devices to SESO

230

(1)

9.4.2 Fabricated SESO Transistor

231

(1)

9.5 SESO Memory

232

(4)

9.6 Memory-Technology Comparison

236

(1)

9.7 SESO as On-Chip RAM Component

237

(2)

9.8 Conclusions

239

(1)

Acknowledgments

240

(1)

References

240

(3)

Chapter 10 Few Electron Devices and Memory Circuits

243

(38)

Kazuo Nakazato and Haroon Ahmed

10.1 Introduction

243

(1)

10.2 Current Semiconductor Memories

244

(3)

10.2.1 Limitations of the DRAM

244

(2)

10.2.2 DRAM Gain Cell

246

(1)

10.3 A New DRAM Gain Cell - The PLEDM

247

(7)

10.3.1 PLEDTR

248

(5)

10.3.2 PLEDM Cell

253

(1)

10.4 Single-Electron Memory

254

(22)

10.4.1 Single-Electron Devices

256

(1)

10.4.2 Operation Principle of Single-Electron Memory

257

(7)

10.4.2.1 Local Stability

257

(3)

10.4.2.2 Global Stability

260

(4)

10.4.3 Experimental Single-Electron Memory

264

(9)

10.4.3.1 First Experimental Single-Electron Memory

264

(5)

10.4.3.2 Silicon Single-Electron Memory

269

(4)

10.4.4 Single-Electron Memory Array

273

(3)

10.5 Conclusion

276

(1)

References

277

(4)

Chapter 11 Single-Electron Logic Devices

281

(24)

Yasuo Takahashi, Yukinori Ono, Akira Fujiwara, and Hiroshi Inokawa

11.1 Introduction

281

(1)

11.2 Single-Electron Transistor (SET)

282

(4)

11.3 Fabrication of Si SETs

286

(2)

11.4 Logic Circuit Applications of SETs

288

(13)

11.4.1 Fundamentals of SET Logic

289

(1)

11.4.2 Merged SET and MOSFET Logic

290

(2)

11.4.3 CMOS-Type Logic Circuit

292

(2)

11.4.4 Pass-Transistor Logic

294

(2)

11.4.5 Multigate SET

296

(2)

11.4.6 Multiple-Valued Operation

298

(3)

11.5 Conclusion

301

(1)

References

301

(4)

Index

305

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Silicon Nanoelectronics

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