System-on-Chip Test Architectures

Written by a stellar team of field experts, this title is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that allow VSLI designers, DFT practitioners, and students to master quickly System-on-Chip Test architectures, memory, and analog/mixed-signal designs.

Introduction
Digital Test Architectures
Fault-Tolerant Design
SOC/NOC Test Architectures
SIP Test Architectures
Delay Testing
Low-Power Testing
Coping with Physical Failures, Soft Errors, and Reliability Issues
Design for Manufacturability and Yield
Design for Debug and Diagnosis
Software-Based Self-Testing
FPGA Testing
MEMS Testing
High-Speed I/O Interface
Analog and Mixed-Signal Test Architectures
RF Testing
Testing Aspects of Nanotechnology Trends
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System-on-Chip Test Architectures

Summary

Table of Contents

Supplemental Materials