Transient-Induced Latchup in CMOS Integrated

The book all Semiconductor device engineers must read to gain a practical feel for latchup-induced failure to produce lower-cost and higher-density chips.

Ming-Dou Ker is a Professor of Electronics Engineering at National

Chiao-Tung

University, where he also serves as the Director of the College of Electrical Engineering and Computer Science Master's Degree Program. He is also the Associate Executive Director of Taiwan's National Science and Technology Program on System-on-Chip, and in the past has worked as the Department Manager in the VLSI Design Division of the Computer and Communication Research Laboratories (CCL), Industrial Technology Research Institute (ITRI). Ker has published 300 technical papers in international journals and conferences related to reliability and quality design for circuits and systems in CMOS technology. He has also proposed many inventions to improve reliability and quality of integrated circuits, generating 125 U.S. patents and 135 Taiwan patents in Taiwan. As an active member of the global IEEE community, he has been Technical Program Committee and Session Chair of numerous international conferences and was selected as the Distinguished Lecturer in IEEE Circuits and Systems Society for year 2006-2007. In 2007 Ker was named IEEE Fellow for his contributions to electrostatic protection in integrated circuits, and performance optimization of VLSI micro-systems. He holds a Ph.D. from the Institute of Electronics,

National

Chiao-Tung

University

.

Preface	p. xi
Introduction	p. 1
Latchup Overview	p. 1
Background of TLU	p. 7
Categroies of TLU-Triggering Modes	p. 7
Power-On Transition	p. 7
Transmission Line Reflections	p. 8
Supply Voltage Overshoots	p. 11
Cable Discharge Event	p. 12
System-Level ESD Event	p. 13
TLU Standard Practice	p. 16
References	p. 19
Physical Mechanism of TLU under the System-Level ESD Test	p. 23
Background	p. 23
TLU in the System-Level ESD Test	p. 24
Test Structure	p. 26
Measurement Setup	p. 28
Device Simulation	p. 30
Latchup DC I-V Characteristics	p. 32
Negative VCharge	p. 32
Positive VCharge	p. 35
A More Realistic Case	p. 37
TLU Measurement	p. 38
Latchup DC I-V Characteristics	p. 38
Negative VCharge	p. 39
Positive VCharge	p. 39
Discussion	p. 41
Dominant Parameter to Induce TLU	p. 41
Transient Responses on the Minority Carriers Stored within the SCR	p. 43
Conclusion	p. 44
References	p. 44
Component-Level Measurement for TLU under System-Level ESD Considerations	p. 47
Background	p. 47
Component-Level TLU Measurement Setup	p. 48
Influence of the Current-Blocking Diode and Current-Limiting Resistance on the Bipolar Trigger Waveforms	p. 49
Positive VCharge	p. 51
Negative VCharge	p. 51
Influence of the Current-Blocking Diode and Current-Limiting Resistance on the TLU Level	p. 54
Latchup DC I-V Characteristics	p. 54
Positive TLU Level	p. 55
Negative TLU Level	p. 57
Verification of Device Simulation	p. 59
Dependences of the Current-Blocking Diode on TLU Level	p. 59
Dependences of Current-Limiting Resistance of TLU Level	p. 62
Suggested Component-Level TLU Measurement Setup	p. 62
TLU Verification on Real Circuits	p. 63
Evaluation on Board-Level Noise Filters to Suppress TLU	p. 66
TLU Transient Waveforms of the Ring Oscillator	p. 69
TLU Level of the Ring Oscillator with Noise Filters	p. 70
Conclusion	p. 72
References	p. 73
TLU Dependency on Power-Pin Damping Frequency and Damping Factor in CMOS Integrated Circuits	p. 75
Examples of Different DFreq and DFactor in the System-Level ESD Test	p. 76
TLU Dependency on DFreq and DFactor	p. 80
Relations between DFactor and Minimum Positive (Negative) VP to Initiate TLU	p. 80
Relations between DFreq and Minimum Positive (Negative) VP to Initiate TLU	p. 82
Relations between DFactor and Minimum (Maximum) DFreq to Initiate TLU	p. 84
Experimental Verification on TLU	p. 86
Suggested Guidelines for TLU Prevention	p. 89
Conclusion	p. 92
References	p. 93
TLU in CMOS ICs in the Electrical Fast Transient Test	p. 95
Electrical Fast Transient Test	p. 95
Test Structure	p. 98
Experimental Measurements	p. 102
Negative EFT Voltage	p. 103
Positive EFT Voltage	p. 104
Physical Mechanism of TLU in the EFT Test	p. 105
Evaluation on Board-Level Noise Filters to Suppress TLU in the EFT Test	p. 106
Capacitor Filter, LC-Like Filter, and ?-Section Filter	p. 106
Ferrite Bead, TVS, and Hybrid Type Filiters	p. 109
Discussion	p. 111
Conclusion	p. 112
References	p. 112
Methodology on Extracting Compact Layout Rules for Latchup Prevention	p. 113
Introduction	p. 113
Latchup Test	p. 114
Latchup Testing Classification	p. 114
Trigger Current Test	p. 115
VSupply Over-Voltage Test	p. 117
Extraction of Layout Rules for I/O Cells	p. 121
Latchup in I/O Cells	p. 121
Design of Test Structure for I/O Cells	p. 124
Latchup Immunity Dependency of I/O Cells	p. 125
Extraction of Layout Rules for Internal Circuits	p. 129
Latchup in Internal Circuits	p. 129
Design of Test Structure for Internal Circuits	p. 130
Latchup Immunity Dependency of the Internal Circuits	p. 131
Extraction of Layout Rules between I/O Cells and Internal Ciruits	p. 136
Layout Considerations between I/O Cells and Internal Circuits	p. 136
Design of Test Structure between I/O Cells and Internal Circuits	p. 139
Threshold Latchup Trigger Current Dependency	p. 141
Conclusion	p. 148
References	p. 149
Special Layout Issues for Latchup Prevention	p. 151
Latchup between Two Different Power Domanins	p. 151
Practical Examples	p. 152
Suggested Solutions	p. 156
Latchup in Internal Circuits Adjacent to Power-Rail ESD Clamp Circuits	p. 156
Practical Examples	p. 157
Suggested Solutions	p. 159
Unexpected Trigger Point to Initiate Latchup in Internal Circuits	p. 159
Practical Examples	p. 161
Suggested Solutions	p. 165
Other Unexpected Latchup Paths in CMOS ICs	p. 165
Conclusion	p. 167
References	p. 168
TLU Prevention in Power-Rail ESD Clamp Circuits	p. 169
In LV CMOS ICs	p. 169
Power-Rail ESD Clamp Circuits	p. 171
TLU-Like Issues in LV Power-Rail ESD Clamp Ciricuits	p. 174
Design of TLU-Free Power-Rail ESD Clamp Circuits	p. 183
In HV CMOS ICs	p. 189
High-Voltage ESD Protection Devices	p. 190
Design of TLU-Free Power-Rail ESD Clamp Circuits	p. 197
Conclusion	p. 204
References	p. 205
Summary	p. 207
TLU in CMOS ICs	p. 207
Extraction of Compact and Safe Layout Rules for Latchup Prevention	p. 209
Practical Application-Extractions of Latchup Design Rules in a 0.18-µm 1.8 V/3.3 V Silicided CMOS Process	p. 211
for I/O Cells	p. 211
Nomenclature	p. 211
I/O Cells with a Double Guard Rings	p. 212
I/O Cells with a Single Guard Ring	p. 215
Suggested Layout Rules for I/O Cells	p. 221
for Internal Circuits	p. 223
Nomenclature	p. 223
Design of Test Structures	p. 223
Latchup Immunity Dependency of Internal Circuits	p. 224
Siggested Layout Rules for Internal Circuits	p. 226
for between I/O and Internal Circuits	p. 226
Normenclature	p. 226
I/O and Internal Circuits (SCR)	p. 227
I/O and the Internal Circuits (Ring Oscillator)	p. 233
Suggested Layout Rules for between I/O and the Internal Circuits	p. 235
For Circuits across Two Different Power Domains	p. 237
Nomenclature	p. 237
Design of Test Structures	p. 237
Latchup Immunity Dependency between Two Different Power Domains	p. 241
Suggested Layout Rules between Two Different Power Domains	p. 242
Suggested Layout Guidelines	p. 244
Latchup Design Guidelines for I/O Circuits 244
Latchup Design Guidelines for between I/O and the Internal Circuits	p. 245
Latchup Design Guidelines for Internal Circuits	p. 246
Latchup Design Guidelines for Circuits across Two Different Power Domains	p. 246
Index	p. 247
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Transient-Induced Latchup in CMOS Integrated Circuits

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