Vhdl for Engineers

This book teaches readers how to design and simulate digital systems using the hardware description language, VHDL. Focus is placed on writing VHDL design decriptions, VHDL testbenches, and the steps in VHDL/PLD (programmable logic devices) design methodology.Topics include: Digital Design using VHDL and PLDs; Entities, Architectures, and Coding Styles; Signals and Data Types; Dataflow and Behavioral Style Combinational Design; Event-Driven Simulation; Testbenches for Combinational Designs; Latches and Flip-Flops; Mulitbit Latches, Registers, Counters, and Memory; Finite State Machines; ASM Charts and RTL Design; Subprograms; Packages; Testbenches for Sequential Systems; Modular Design and Hierarchy. More than 275 block diagrams, logic diagrams, and timing waveforms and 180+ program listings illustrate the design concepts. The book includes the Aldec Active-HDLtrade; 7.2 Student Edition Software. This book is suitable for anyone with a basic understanding of logic design and a minimal background in programming who desires to lean how to design digital systems using VHDL. No prior experience with VHDL is required.

Preface
Digital Design Using VHDL and PLDs	p. 1
VHDL/PLD Design Methodology	p. 1
Requirements Analysis and Specification	p. 5
VHDL Design Description	p. 6
Verification Using Simulation	p. 11
Testbenches	p. 13
Functional (Behavioral) Simulation	p. 16
Programmable Logic Devices (PLDs)	p. 18
SPLDs and the 22V10	p. 21
Logic Synthesis for the Target PLD	p. 27
Place-and-Route and Timing Simulation	p. 31
Programming and Verifying a Target PLD	p. 37
VHDL/PLD Design Methodology Advantages	p. 38
VHDLrsquo;s Development	p. 39
VHDL for Synthesis versus VHDL for Simulation	p. 39
This Bookrsquo;s Primary Objective	p. 40
Entities , Architectures , and Coding Styles	p. 44
Design Units, Library Units, and Design Entities	p. 44
Entity Declaration	p. 45
VHDL Syntax Definitions	p. 47
Port Modes	p. 50
Architecture Body	p. 53
Coding Styles	p. 55
Synthesis Results versus Coding Style	p. 66
Levels of Abstraction and Synthesis	p. 69
Design Hierarchy and Structural Style	p. 71
Signals and Data Types	p. 82
Object Classes and Object Types	p. 82
Signal Objects	p. 84
Scalar Types	p. 88
Type Std_Logic	p. 93
Scalar Literals and Scalar Constants	p. 99
Composite Types	p. 100
Arrays	p. 101
Types Unsigned and Signed	p. 107
Composite Literals and Composite Constants	p. 110
Integer Types	p. 112
Table of Contents provided by Publisher. All Rights Reserved.

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Table of Contents

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