VLSI Circuit Design Methodology Demystified A

This book was written to arm engineers qualified and knowledgeable in the area of VLSI circuits with the essential knowledge they need to get into this exciting field and to help those already in it achieve a higher level of proficiency. Few people truly understand how a large chip is developed, but an understanding of the whole process is necessary to appreciate the importance of each part of it and to understand the process from concept to silicon. It will teach readers how to become better engineers through a practical approach of diagnosing and attacking real-world problems.

Liming Xiu is a Design Engineer and a Senior Member of Technical Staff (SMTS) at Texas Instruments, Inc. His interests include digital and mixed-signal integrated circuit design and VLSI physical design. He has worked on various mixed-signal devices, including video decoders, 3-D graphics controllers, and HDTV decoders, as physical design lead. He is also a Phase Lock Loop (PLL) expert. He is the inventor of "Flying-Adder" frequency and phase synthesis architecture, which has been used in many commercial products. He has eleven granted or pending U.S. patents. He is a Senior Member of the IEEE and the general chair of the IEEE Circuit and Systems Society, Dallas Chapter.

Foreword	p. xi
Foreword	p. xiii
Preface	p. xv
Acknowledgments	p. xvii
The Big Picture	p. 1
What is a chip?	p. 1
What are the requirements of a successful chip design?	p. 3
What are the challenges in today's very deep submicron (VDSM), multimillion gate designs?	p. 4
What major process technologies are used in today's design environment?	p. 5
What are the goals of new chip design?	p. 8
What are the major approaches of today's very large scale integration (VLSI) circuit design practices?	p. 9
What is standard cell-based, application-specific integrated circuit (ASIC) design methodology?	p. 11
What is the system-on-chip (SoC) approach?	p. 12
What are the driving forces behind the SoC trend?	p. 15
What are the major tasks in developing a SoC chip from concept to silicon?	p. 15
What are the major costs of developing a chip?	p. 16
The Basics of the CMOS Process and Devices	p. 17
What are the major process steps in building MOSFET transistors?	p. 17
What are the two types of MOSFET transistors?	p. 19
What are base layers and metal layers?	p. 20
What are wafers and dies?	p. 24
What is semiconductor lithography?	p. 28
What is a package?	p. 33
The Challenges in VLSI Circuit Design	p. 41
What is the role of functional verification in the IC design process?	p. 41
What are some of the design integrity issues?	p. 44
What is design for testability?	p. 46
Why is reducing the chip's power consumption so important?	p. 48
What are some of the challenges in chip packaging?	p. 49
What are the advantages of design reuse?	p. 50
What is hardware/software co-design?	p. 51
Why is the clock so important?	p. 54
What is the leakage current problem?	p. 57
What is design for manufacturability?	p. 60
What is chip reliability?	p. 62
What is analog integration in the digital environment?	p. 65
What is the role of EDA tools in IC design?	p. 67
What is the role of the embedded processor in the SoC environment?	p. 69
Cell-Based ASIC Design Methodology	p. 73
What are the major tasks and personnel required in a chip design project?	p. 73
What are the major steps in ASIC chip construction?	p. 74
What is the ASIC design flow?	p. 75
What are the two major aspects of ASIC design flow?	p. 77
What are the characteristics of good design flow?	p. 80
What is the role of market research in an ASIC project?	p. 81
What is the optimal solution of an ASIC project?	p. 82
What is system-level study of a project?	p. 84
What are the approaches for verifying design at the system level?	p. 85
What is register-transfer-level (RTL) system-level description?	p. 86
What are methods of verifying design at the register-transfer-level?	p. 87
What is a test bench?	p. 88
What is code coverage?	p. 89
What is functional coverage?	p. 89
What is bug rate convergence?	p. 90
What is design planning?	p. 91
What are hard macro and soft macro?	p. 92
What is hardware description language (HDL)?	p. 92
What is register-transfer-level (RTL) description of hardware?	p. 93
What is standard cell? What are the differences among standard cell, gate-array, and sea-of-gate approaches?	p. 94
What is an ASIC library?	p. 103
What is logic synthesis?	p. 105
What are the optimization targets of logic synthesis?	p. 106
What is schematic or netlist?	p. 107
What is the gate count of a design?	p. 111
What is the purpose of test insertion during logic synthesis?	p. 111
What is the most commonly used model in VLSI circuit testing?	p. 112
What are controllability and observability in a digital circuit?	p. 114
What is a testable circuit?	p. 115
What is the aim of scan insertion?	p. 116
What is fault coverage? What is defect part per million (DPPM)?	p. 117
Why is design for testability important for a product's financial success?	p. 119
What is chip power usage analysis?	p. 120
What are the major components of CMOS power consumption?	p. 121
What is power optimization?	p. 123
What is VLSI physical design?	p. 123
What are the problems that make VLSI physical design so challenging?	p. 124
What is floorplanning?	p. 128
What is the placement process?	p. 131
What is the routing process?	p. 133
What is a power network?	p. 135
What is clock distribution?	p. 139
What are the key requirements for constructing a clock tree?	p. 143
What is the difference between time skew and length skew in a clock tree?	p. 145
What is scan chain?	p. 149
What is scan chain reordering?	p. 151
What is parasitic extraction?	p. 152
What is delay calculation?	p. 155
What is back annotation?	p. 156
What kind of signal integrity problems do place and route tools handle?	p. 156
What is cross-talk delay?	p. 157
What is cross-talk noise?	p. 158
What is IR drop?	p. 159
What are the major netlist formats for design representation?	p. 162
What is gate-level logic verification before tapeout?	p. 162
What is equivalence check?	p. 163
What is timing verification?	p. 164
What is design constraint?	p. 165
What is static timing analysis (STA)?	p. 165
What is simulation approach on timing verification	p. 169
What is the logical-effort-based timing closure approach?	p. 173
What is physical verification?	p. 178
What are design rule check (DRC), design verification (DV), and geometry verification (GV)?	p. 179
What is schematic verification (SV) or layout versus schematic (LVS)?	p. 181
What is automatic test pattern generation (ATPG)?	p. 182
What is tapeout?	p. 184
What is yield?	p. 184
What are the qualities of a good IC implementation designed?	p. 187
Conclusion	p. 189
Acronyms	p. 191
Bibliography	p. 195
Index	p. 199
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VLSI Circuit Design Methodology Demystified A Conceptual Taxonomy

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