VLSI Test Principles and Architectures

, by Wang; Wu; Wen; Abdel-Hafez; Bhattacharya; Chatterjee; Chen; Cheng; Eklow; Hsiao; Huang; Huang; Jone; Kapur; Keller; Lee; Li; Li; Li; Mak; Min; Nadeau-Dostie; Nourani; Rajski; Stroud; Volkerink; Walker; Wu; Touba

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ISBN: 9780123705976 | 0123705975
Cover: Hardcover
Copyright: 7/7/2006

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This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. · Most up-to-date coverage of design for testability. · Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. · Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures. · Lecture slides and exercise solutions for all chapters are now available. · Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website.

Preface

xxi

In the Classroom

xxiv

Acknowledgments

xxv

Contributors

xxvii

About the Editors

xxix

Introduction

(36)

Yinghua Min

Charles Stroud

Importance of Testing

(1)

Testing During the VLSI Lifecycle

(6)

VLSI Development Process

(1)

Design Verification

(1)

Yield and Reject Rate

(1)

Electronic System Manufacturing Process

(1)

System-Level Operation

(2)

Challenges in VLSI Testing

(14)

Test Generation

(2)

Fault Models

(1)

Stuck-At Faults

(3)

Transistor Faults

(1)

Open and Short Faults

(3)

Delay Faults and Crosstalk

(1)

Pattern Sensitivity and Coupling Faults

(1)

Analog Fault Models

(1)

Levels of Abstraction in VLSI Testing

(3)

(1)

Gate Level

(1)

Switch Level

(1)

Physical Level

(1)

Historical Review of VLSI Test Technology

(8)

Automatic Test Equipment

(2)

Automatic Test Pattern Generation

(1)

Fault Simulation

(1)

Digital Circuit Testing

(1)

Analog and Mixed-Signal Circuit Testing

(1)

Design for Testability

(2)

Board Testing

(1)

Boundary Scan Testing

(1)

Concluding Remarks

(1)

Exercises

(4)

Acknowledgments

(1)

References

(3)

Design for Testability

(68)

Laung-Terng (L.-T.) Wang

Xiaoqing Wen

Khader S. Abdel-Hafez

Introduction

(3)

Testability Analysis

(10)

SCOAP Testability Analysis

(1)

Combinational Controllability and Observability Calculation

(2)

Sequential Controllability and Observability Calculation

(2)

Probability-Based Testability Analysis

(2)

Simulation-Based Testability Analysis

(1)

RTL Testability Analysis

(2)

Design for Testability Basics

(5)

Ad Hoc Approach

(1)

Test Point Insertion

(2)

Structured Approach

(2)

Scan Cell Designs

(4)

Muxed-D Scan Cell

(1)

Clocked-Scan Cell

(1)

LSSD Scan Cell

(2)

Scan Architectures

(11)

Full-Scan Design

(1)

Muxed-D Full-Scan Design

(3)

Clocked Full-Scan Design

(1)

LSSD Full-Scan Design

(2)

Partial-Scan Design

(3)

Random-Access Scan Design

(3)

Scan Design Rules

(6)

Tristate Buses

(1)

Bidirectional I/O Ports

(1)

Gated Clocks

(3)

Derived Clocks

(1)

Combinational Feedback Loops

(1)

Asynchronous Set/Reset Signals

(1)

Scan Design Flow

(11)

Scan Design Rule Checking and Repair

(1)

Scan Synthesis

(1)

Scan Configuration

(3)

Scan Replacement

(1)

Scan Reordering

(1)

Scan Stitching

(1)

Scan Extraction

(1)

Scan Verification

(1)

Verifying the Scan Shift Operation

(1)

Verifying the Scan Capture Operation

(1)

Scan Design Costs

(1)

Special-Purpose Scan Designs

(5)

Enhanced Scan

(1)

Snapshot Scan

(2)

Error-Resilient Scan

(2)

RTL Design for Testability

(3)

RTL Scan Design Rule Checking and Repair

(1)

RTL Scan Synthesis

(1)

RTL Scan Extraction and Scan Verification

(1)

Concluding Remarks

(1)

Exercises

(9)

Acknowledgments

(1)

References

(6)

Logic and Fault Simulation

105

(56)

Jiun-Lang Huang

James C.-M. Li

Duncan M. (Hank) Walker

Introduction

106

(2)

Logic Simulation for Design Verification

106

(1)

Fault Simulation for Test and Diagnosis

107

(1)

Simulation Models

108

(13)

Gate-Level Network

109

(1)

Sequential Circuits

109

(1)

Logic Symbols

110

(1)

Unknown State u

111

(2)

High-Impedance State Z

113

(1)

Intermediate Logic States

114

(1)

Logic Element Evaluation

114

(1)

Truth Tables

115

(1)

Input Scanning

115

(1)

Input Counting

116

(1)

Parallel Gate Evaluation

116

(2)

Timing Models

118

(1)

Transport Delay

118

(1)

Inertial Delay

119

(1)

Wire Delay

119

(1)

Functional Element Delay Model

120

(1)

Logic Simulation

121

(11)

Compiled-Code Simulation

121

(1)

Logic Optimization

121

(2)

Logic Levelization

123

(1)

Code Generation

124

(1)

Event-Driven Simulation

125

(1)

Nominal-Delay Event-Driven Simulation

126

(3)

Compiled-Code Versus Event-Driven Simulation

129

(1)

Hazards

130

(1)

Static Hazard Detection

131

(1)

Dynamic Hazard Detection

132

(1)

Fault Simulation

132

(22)

Serial Fault Simulation

133

(2)

Parallel Fault Simulation

135

(1)

Parallel Fault Simulation

135

(2)

Parallel-Pattern Fault Simulation

137

(2)

Deductive Fault Simulation

139

(4)

Concurrent Fault Simulation

143

(3)

Differential Fault Simulation

146

(2)

Fault Detection

148

(1)

Comparison of Fault Simulation Techniques

149

(2)

Alternatives to Fault Simulation

151

(1)

Toggle Coverage

151

(1)

Fault Sampling

151

(1)

Critical Path Tracing

152

(1)

Statistical Fault Analysis

153

(1)

Concluding Remarks

154

(1)

Exercises

155

(6)

References

158

(3)

Test Generation

161

(102)

Michael S. Hsiao

Introduction

161

(2)

Random Test Generation

163

(3)

Exhaustive Testing

166

(1)

Theoretical Background: Boolean Difference

166

(3)

Untestable Faults

168

(1)

Designing a Stuck-At ATPG for Combinational Circuits

169

(25)

A Naive ATPG Algorithm

169

(3)

Backtracking

172

(1)

A Basic ATPG Algorithm

173

(4)

D Algorithm

177

(5)

PODEM

182

(4)

FAN

186

(1)

Static Logic Implications

187

(4)

Dynamic Logic Implications

191

(3)

Designing a Sequential ATPG

194

(6)

Time Frame Expansion

194

(2)

5-Valued Algebra Is Insufficient

196

(1)

Gated Clocks and Multiple Clocks

197

(3)

Untestable Fault Identification

200

(7)

Multiple-Line Conflict Analysis

203

(4)

Designing a Simulation-Based ATPG

207

(11)

Overview

208

(1)

Genetic-Algorithm-Based ATPG

208

(4)

Issues Concerning the GA Population

212

(1)

Issues Concerning GA Parameters

213

(1)

Issues Concerning the Fitness Function

213

(2)

CASE Studies

215

(3)

Advanced Simulation-Based ATPG

218

(8)

Seeding the GA with Helpful Sequences

218

(4)

Logic-Simulation-Based ATPG

222

(3)

Spectrum-Based ATPG

225

(1)

Hybrid Deterministic and Simulation-Based ATPG

226

(5)

ALT-TEST Hybrid

228

(3)

ATPG for Non-Stuck-At Faults

231

(15)

Designing an ATPG That Captures Delay Defects

231

(2)

Classification of Path-Delay Faults

233

(3)

ATPG for Path-Delay Faults

236

(2)

ATPG for Transition Faults

238

(2)

Transition ATPG Using Stuck-At ATPG

240

(1)

Transition ATPG Using Stuck-At Vectors

240

(1)

Transition Test Chains via Weighted Transition Graph

241

(3)

Bridging Fault ATPG

244

(2)

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VLSI Test Principles and Architectures

Summary

Table of Contents

Supplemental Materials