Wafer-level Testing and Test During Burn-in for Integrated Circuits

, by Bahukudumbi, Sudarshan; Chakrabarty, Krishnendu

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ISBN: 9781596939899 | 1596939893
Cover: Hardcover
Copyright: 2/28/2010

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Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This hands-on resource provides a comprehensive analysis of these methods, showing how wafer-level testing during burn-in (WLTBI) helps lower product cost in semiconductor manufacturing. Engineers learn how to implement the testing of integrated circuits at the wafer-level under various resource constraints. Moreover, this unique book helps practitioners address the issue of enabling next generation products with previous generation testers. Practitioners also find expert insights on current industry trends in WLTBI test solutions.

Preface	p. xiii
Acknowledgments	p. xv
Introduction	p. 1
Background	p. 4
System-Level Design-for-Test and Test Scheduling for Core-Based SoCs	p. 4
Wafer-Level Test During Burn-In	p. 6
Scan Design	p. 9
Key Drivers for Wafer-Level Test and Burn-In	p. 9
Challenges Associated with Wafer Sort	p. 10
Emergence of KGDs	p. 11
WLTBI: Industry Adoption and Challenges	p. 11
Wafer-Level Test Planning for Core-Based SoCs	p. 16
Wafer-Level Defect Screening for Mixed-Signal SoCs	p. 17
WLTBI of Core-Based SoCs	p. 17
Power Management for WLTBI	p. 18
How This Book Is Organized	p. 18
References	p. 20
Wafer-Level Test and Burn-In Industry Practices and Trends	p. 25
Overview and Definitions	p. 25
Status of Wafer-Level Test and WLBI	p. 29
Wafer-Level Burn-In	p. 31
Doing Both Wafer-Level Test and Wafer-Level Burn-In	p. 33
Practical Matters	p. 34
Volumes Needed	p. 34
Power per Die and per Wafer	p. 36
Types of Die That Can Be Tested and Burned-In	p. 36
Functional Tests Versus Parametric Tests	p. 36
Number of Contacts per Die	p. 37
Number of Signal Channels Needed	p. 37
Single-Pass Versus Multiple Pass	p. 38
Maximum Force per Wafer	p. 38
Contact Method	p. 39
Contact Life	p. 40
Minimizing Costs for SDBs and Contactors	p. 41
Bumped Wafers Versus Wafers with Bond Pads	p. 41
Pitch	p. 41
Pad Size	p. 42
Coplanarity	p. 43
Background (Thinned) Wafers and Plastic-Backed Wafers	p. 43
More Than One Die Type on the Wafer	p. 43
Changing Cartridges	p. 43
Test Electronics	p. 44
Die Power and Shorted Die	p. 44
Current per Die and per Wafer	p. 44
Voltage Levels Needed	p. 45
Clock and Pattern Frequencies	p. 45
Wafer Maps and Binning	p. 45
Future Projections	p. 45
References	p. 46
Resource-Constrained Testing of Core-Based SoCs	p. 49
Defect Probability Estimation for Embedded Cores	p. 51
Unified Negative-Binomial Model for Yield Estimation	p. 51
Procedure to Determine Core Defect Probabilities	p. 52
Test-Length Selection for Wafer-Level Test	p. 56
Test-Length Selection Problem: $$$TLS	p. 60
Efficient Heuristic Procedure	p. 62
Greedy Heuristic Procedure	p. 64
Experimental Results	p. 65
Approximation Error in P^r_S Due to Taylor Series Approximation	p. 68
Test Data Serialization	p. 72
Test-Length and TAM Optimization Problem: $$$TLTWS	p. 74
Experimental Results: $$$TLTWS	p. 76
Enumeration-Based TAM Width and Test-Length Selection	p. 80
TAM Width and Test-Length Selection Based on Geometric Programming	p. 83
Approximation Error in P^r_S	p. 87
Summary	p. 88
References	p. 89
Defect Screening for "Big-D/Small-A" Mixed-Signal SoCs	p. 91
Test Wrapper for Analog Cores	p. 92
Analog Test Wrapper Modes	p. 94
Wafer-Level Defect Screening: Mixed-Signal Cores	p. 94
Signature Analysis: Mean-Signature-Based Correlation (MSBC)	p. 96
Signature Analysis: Golden-Signature-Based Correlation (GSBC)	p. 97
Generic Cost Model	p. 100
Correction Factors: Test Escapes and Yield Loss	p. 100
Cost Model: Generic Framework	p. 102
Overall Cost Components	p. 103
Cost Model: Quantitative Analysis	p. 104
Cost Model: Results for ASIC Chip K	p. 105
Cost Model: Results Considering Failures Due to Both Digital and Mixed-Signal Cores	p. 106
Cost Model: Results Considering Failure Distributions	p. 108
Summary	p. 113
Acknowledgments	p. 114
References	p. 114
Wafer-Level Test During Burn-In: Test Scheduling for Core-Based SOCs	p. 117
Cycle-Accurate Power Modeling	p. 119
Transitions in a Scan Chain	p. 120
Transitions in Wrapper Chains	p. 124
Test Scheduling for WLTBI	p. 125
Graph-Matching-Based Approach for Test Scheduling	p. 126
Heuristic Procedure to Solve P_Core-Order	p. 131
Baseline Methods	p. 132
Experimental Results	p. 132
Summary	p. 139
Acknowledgments	p. 139
References	p. 139
Wafer-Level Test During Bum-In: Power Management by Test-Pattern Ordering	p. 141
Background: Cycle-Accurate Power Modeling	p. 142
Scan-Chain Transition-Count Calculation	p. 142
Test-Pattern Ordering Problem: P_TPO	p. 144
Computational Complexity of _TPO	p. 147
Heuristic Methods for Test-Pattern Ordering	p. 148
Baseline Approaches	p. 150
Baseline Method 1: Average Power Consumption	p. 150
Baseline Method 2: Peak Power Consumption	p. 151
Experimental Results	p. 151
Summary	p. 155
References	p. 160
Wafer-Level Test During Burn-In: Power Management by Test-Pattern Manipulation	p. 163
Minimum-Variation X-Fill Problem: P_MVF	p. 164
Metrics: Variation in Power Consumption During Test	p. 164
Outline of Proposed Method	p. 165
Framework to Control Power Variation for WLTBI	p. 166
Minimum- Variation X -Filling	p. 166
Eliminating Capture-Power Violations	p. 169
Test-Pattern Ordering for WLTBI	p. 170
Complete Procedure	p. 171
Baseline Approaches	p. 172
Baseline Method 1: Adjacent Fill	p. 172
Baseline Method 2: 0-Fill	p. 174
Baseline Method 3:1-Fill	p. 174
Baseline Method 4: ATPG-Compacted Test Sets	p. 174
Experimental Results	p. 175
Summary	p. 181
References	p. 182
Conclusions	p. 183
Summary	p. 183
Future Work	p. 185
Integrated Test-Length and Test-Pattern Selection for Core-Based SoCs	p. 185
Multiple Scan-Chain Design for WLTBI	p. 186
Layout-Aware SoC Test Scheduling for WLTBI	p. 186
References	p. 187
List of Symbols	p. 189
List of Acronyms	p. 191
About the Authors	p. 195
Index	p. 197
Table of Contents provided by Ingram. All Rights Reserved.

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Wafer-level Testing and Test During Burn-in for Integrated Circuits

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Wafer-level Testing and Test During Burn-in for Integrated Circuits

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