Digital Logic and Microprocessor Design with VHDL

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ISBN: 9780534465933 | 0534465935
Cover: Hardcover
Copyright: 2/18/2005

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This book will teach students how to design digital logic circuits, specifically combinational and sequential circuits. Students will learn how to put these two types of circuits together to form dedicated and general-purpose microprocessors. This book is unique in that it combines the use of logic principles and the building of individual components to create data paths and control units, and finally the building of real dedicated custom microprocessors and general-purpose microprocessors. After understanding the material in the book, students will be able to design simple microprocessors and implement them in real hardware.

Preface

About the Author

xix

Designing Microprocessors

(16)

Overview of a Microprocessor

(2)

Design Abstraction Levels

(2)

Examples of a 2-to-1 Multiplexer

(3)

Behavioral Level

(1)

Gate Level

(2)

Transistor Level

(1)

Introduction to VHDL

(3)

Synthesis

(1)

Going Forward

(1)

Summary Checklist

(2)

Problems

(1)

Digital Circuits

(37)

Binary Numbers

(4)

Binary Switch

(1)

Basic Logic Operators and Logic Expressions

(1)

Truth Tables

(1)

Boolean Algebra and Boolean Functions

(8)

Boolean Algebra

(3)

Duality Principle

(1)

Boolean Functions and their Inverses

(4)

Minterms and Maxterms

(5)

Minterms

(3)

Maxterms

(2)

Canonical, Standard, and Non-Standard Forms

(1)

Logic Gates and Circuit Diagrams

(4)

Designing a Car Security System

(2)

VHDL for Digital Circuits

(4)

VHDL Code for a 2-Input NAND Gate

(1)

VHDL Code for a 3-Input NOR Gate

(1)

VHDL Code for a Function

(1)

Summary Checklist

(1)

Problems

(4)

Combinational Circuits

(44)

Analysis of Combinational Circuits

(5)

Using a Truth Table

(3)

Using a Boolean Function

(1)

Synthesis of Combinational Circuits

(3)

Technology Mapping

(4)

Minimization of Combinational Circuits

(10)

Karnaugh Maps

(7)

Don't-Cares

(1)

Tabulation Method

(2)

Timing Hazards and Glitches

(3)

Using Glitches

(1)

BCD to 7-Segment Decoder

(2)

VHDL for Combinational Circuits

(9)

Structural BCD to 7-Segment Decoder

(5)

Dataflow BCD to 7-Segment Decoder

(1)

Behavioral BCD to 7-Segment Decoder

(2)

Summary Checklist

(1)

Problems

(6)

Standard Combinational Components

(47)

Signal Naming Conventions

(1)

Adder

100

(5)

Full Adder

100

(1)

Ripple-Carry Adder

101

(1)

Carry-Lookahead Adder

102

(3)

Two's Complement Binary Numbers

105

(3)

Subtractor

108

(1)

Adder-Subtractor Combination

109

(5)

Arithmetic Logic Unit

114

(3)

Decoder

117

(5)

Encoder

122

(2)

Priority Encoder

123

(1)

Multiplexer

124

(4)

Using Multiplexers to Implement a Function

128

(1)

Tri-State Buffer

128

(2)

Comparator

130

(4)

Shifter

134

(2)

Barrel Shifter

135

(1)

Multiplier

136

(3)

Summary Checklist

139

(1)

Problems

139

(6)

Implementation Technologies

145

(33)

Physical Abstraction

146

(1)

Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET)

147

(1)

CMOS Logic

148

(2)

CMOS Circuits

150

(9)

CMOS Inverter

151

(1)

CMOS NAND Gate

152

(2)

CMOS AND Gate

154

(1)

CMOS NOR and OR Gates

155

(1)

Transmission Gate

155

(1)

2-Input Multiplexer CMOS Circuit

156

(2)

CMOS XOR and XNOR Gates

158

(1)

Analysis of CMOS Circuits

159

(2)

Using ROMs to Implement a Function

161

(3)

Using PLAs to Implement a Function

164

(4)

Using PALs to Implement a Function

168

(2)

Complex Programmable Logic Device (CPLD)

170

(3)

Field Programmable Gate Array (FPGA)

173

(2)

Summary Checklist

175

(1)

Problems

175

(3)

Latches and Flip-Flops

178

(35)

Bistable Element

180

(1)

SR Latch

181

(3)

SR Latch with Enable

184

(1)

D Latch

185

(1)

D Latch with Enable

186

(1)

Clock

187

(1)

D Flip-Flop

188

(5)

Alternative Smaller Circuit

191

(2)

D Flip-Flop with Enable

193

(1)

Asynchronous Inputs

193

(2)

Description of a Flip-Flop

195

(2)

Characteristic Table

195

(1)

Characteristic Equation

195

(1)

State Diagram

196

(1)

Excitation Table

196

(1)

Timing Issues

197

(1)

Designing a Car Security System---Version 2

198

(1)

VHDL for Latches and Flip-Flops

199

(7)

Implied Memory Element

199

(2)

VHDL Code for a D Latch with Enable

201

(1)

VHDL Code for a D Flip-Flop

201

(4)

VHDL Code for a D Flip-Flop with Enable and Asynchronous Set and Clear

205

(1)

Other Flip-Flop Types

206

(4)

SR Flip-Flop

206

(2)

JK Flip-Flop

208

(1)

T Flip-Flop

208

(2)

Summary Checklist

210

(1)

Problems

211

(2)

Sequential Circuits

213

(61)

Finite State Machine (FSM) Models

215

(3)

State Diagrams

218

(3)

Analysis of Sequential Circuits

221

(9)

Excitation Equation

222

(1)

Next-State Equation

222

(1)

Next-State Table

222

(2)

Output Equation

224

(1)

Output Table

224

(1)

State Diagram

224

(1)

Analysis of a Moore FSM

225

(3)

Analysis of a Mealy FSM

228

(2)

Synthesis of Sequential Circuits

230

(16)

State Diagram

231

(1)

Next-State Table

232

(2)

Implementation Table

234

(1)

Excitation Equation and Next-State Circuit

235

(1)

Output Table and Equation

235

(1)

FSM Circuit

235

(1)

Synthesis of Moore FSMs

236

(6)

Synthesis of a Mealy FSM

242

(4)

Unused State Encodings and the Encoding of States

246

(3)

Designing a Car Security System---Version 3

249

(1)

VHDL for Sequential Circuits

249

(9)

Optimization for Sequential Circuits

258

(6)

State Reduction

258

(1)

State Encoding

259

(1)

Choice of Flip-Flops

260

(4)

Summary Checklist

264

(1)

Problems

265

(9)

Standard Sequential Components

274

(36)

Registers

275

(2)

Shift Registers

277

(6)

Serial-to-Parallel Shift Register

278

(2)

Serial-to-Parallel and Parallel-to-Serial Shift Register

280

(3)

Counters

283

(11)

Binary Up Counter

283

(3)

Binary Up-Down Counter

286

(3)

Binary Up-Down Counter with Parallel Load

289

(1)

BCD Up Counter

290

(2)

BCD Up-Down Counter

292

(2)

294

(5)

Static Random Access Memory

299

(4)

Larger Memories

303

(4)

More Memory Locations

304

(1)

Wider Bit Width

305

(2)

Summary Checklist

307

(1)

Problems

308

(2)

Datapaths

310

(49)

Designing Dedicated Datapaths

313

(8)

Selecting Registers

317

(1)

Selecting Functional Units

318

(1)

Data Transfer Methods

319

(1)

Generating Status Signals

320

(1)

Using Dedicated Datapaths

321

(1)

Examples of Dedicated Datapaths

322

(12)

Simple IF-THEN-ELSE

323

(2)

Counting 1 to 10

325

(2)

Summation of n Down to 1

327

(1)

Factorial of n

328

(3)

Counting 0's and 1's

331

(3)

General Datapaths

334

(2)

Using General Datapaths

336

(3)

A More Complex General Datapath

339

(5)

Timing Issues

344

(3)

VHDL for Datapaths

347

(7)

Dedicated Datapath

347

(2)

General Datapath

349

(5)

Summary Checklist

354

(1)

Problems

355

(4)

Control Units

359

(58)

Constructing the Control Unit

361

(13)

Counting 1 to 10

362

(5)

Simple IF-THEN-ELSE

367

(7)

Generating Status Signals

374

(10)

Stand-Alone Controllers

384

(20)

Rotating Lights

384

(4)

PS/2 Keyboard Controller

388

(5)

VGA Monitor Controller

393

(11)

ASM Charts and State Action Tables

404

(8)

ASM Charts

406

(4)

State Action Tables

410

(2)

VHDL for Control Units

412

(2)

Summary Checklist

414

(1)

Problems

415

(2)

Dedicated Microprocessors

417

(50)

Manual Construction of a Dedicated Microprocessor

420

(3)

Examples of Manual Designs of Dedicated Microprocessors

423

(29)

Greatest Common Divisor

424

(7)

Summing Input Numbers

431

(7)

High-Low Guessing Game

438

(7)

Finding the Largest Number

445

(7)

VHDL for Dedicated Microprocessors

452

(12)

FSM+D Model

452

(7)

FSMD Model

459

(3)

Behavioral Model

462

(2)

Summary Checklist

464

(1)

Problems

464

(3)

General-Purpose Microprocessors

467

(44)

Overview of the CPU Design

468

(2)

The EC-1 General-Purpose Microprocessor

470

(12)

Instruction Set

470

(2)

Datapath

472

(1)

Control Unit

473

(4)

Complete Circuit

477

(1)

Sample Program

477

(2)

Simulation

479

(1)

Hardware Implementation

480

(2)

The EC-2 General-Purpose Microprocessor

482

(12)

Instruction Set

482

(1)

Datapath

483

(2)

Control Unit

485

(5)

Complete Circuit

490

(1)

Sample Program

490

(3)

Hardware Implementation

493

(1)

VHDL for General-Purpose Microprocessors

494

(13)

Structural FSM+D

494

(10)

Behavioral FSMD

504

(3)

Summary Checklist

507

(1)

Problems

508

(3)

A Schematic Entry---Tutorial 1

511

(14)

Getting Started

512

(1)

Preparing a Folder for the Project

512

(1)

Starting MAX+plus II

512

(1)

Starting the Graphic Editor

513

(1)

Using the Graphic Editor

513

(5)

Drawing Tools

513

(1)

Inserting Logic Symbols

514

(2)

Selecting, Moving, Copying, and Deleting Logic Symbols

516

(1)

Making and Naming Connections

516

(2)

Selecting, Moving and Deleting Connection Lines

518

(1)

Specifying the Top-Level File and Project

518

(1)

Saving the Schematic Drawing

518

(1)

Specifying the Project

519

(1)

Synthesis for Functional Simulation

519

(1)

Circuit Simulation

520

(4)

Selecting Input Test Signals

520

(1)

Customizing the Waveform Editor

521

(1)

Assigning Values to the Input Signals

522

(1)

Saving the Waveform File

523

(1)

Starting the Simulator

523

(1)

Creating and Using the Logic Symbol

524

(1)

B VHDL Entry---Tutorial 2

525

(9)

Getting Started

525

(3)

Preparing a Folder for the Project

525

(1)

Starting MAX+plus II

526

(1)

Creating a Project

527

(1)

Editing the VHDL Source Code

528

(1)

Synthesis for Functional Simulation

528

(1)

Circuit Simulation

529

(5)

Selecting Input Test Signals

529

(1)

Customizing the Waveform Editor

530

(1)

Assigning Values to the Input Signals

531

(1)

Saving the Waveform File

532

(1)

Starting the Simulator

532

(2)

C UP2 Programming---Tutorial 3

534

(23)

Getting Started

535

(1)

Preparing a Folder for the Project

535

(1)

Creating a Project

536

(1)

Viewing the Source File

536

(1)

Synthesis for Programming the PLD

536

(2)

Selecting the Target Device

536

(1)

Synthesis

537

(1)

Circuit Simulation

538

(2)

Mapping the I/O Pins with the Floorplan Editor

540

(3)

Fitting the Netlist and Pins to the PLD

543

(1)

Hardware Setup

544

(2)

Installing the ByteBlaster Driver

544

(1)

Jumper Settings

544

(1)

Hardware Connections

545

(1)

Programming the PLD

546

(1)

Testing the Hardware

547

(1)

MAX7000S EPM7128SLC84-7 Summary

548

(5)

JTAG Jumper Settings

548

(1)

Prototyping Resources for Use

548

(2)

General Pin Assignments

550

(1)

Two Push-Button Switches

550

(1)

16 DIP Switches

551

(1)

16 LEDs

552

(1)

7-Segment LEDs

552

(1)

Clock

553

(1)

FLEX10K EPF10K70RC240--4 Summary

553

(4)

JTAG Jumper Settings

553

(1)

Prototyping Resources for Use

553

(1)

Two Push-Button Switches

553

(1)

8 DIP Switches

554

(1)

7-Segment LEDs

554

(1)

Clock

555

(1)

PS/2 Port

555

(1)

VGA Port

556

(1)

D VHDL Summary

557

(24)

Basic Language Elements

557

(10)

Comments

557

(1)

Identifiers

557

(1)

Data Objects

558

(1)

Data Types

558

(3)

Data Operators

561

(1)

Entity

562

(1)

Architecture

562

(2)

Generic

564

(1)

Package

565

(2)

Dataflow Model---Concurrent Statements

567

(2)

Concurrent Signal Assignment

567

(1)

Conditional Signal Assignment

567

(1)

Selected Signal Assignment

568

(1)

Dataflow Model Sample

568

(1)

Behavioral Model---Sequential Statements

569

(6)

Process

569

(1)

Sequential Signal Assignment

569

(1)

Variable Assignment

570

(1)

Wait

570

(1)

If-Then-Else

570

(1)

Case

571

(1)

Null

571

(1)

For

571

(1)

While

572

(1)

Loop

572

(1)

Exit

572

(1)

572

(1)

Function

573

(1)

Procedure

574

(1)

Behavioral Model Sample

575

(1)

Structural Model---Concurrent Statements

575

(4)

Component Declaration

576

(1)

Port Map

576

(1)

Open

577

(1)

Generate

577

(1)

Structural Model Sample

578

(1)

Conversion Routines

579

(2)

Conv_Integer()

579

(1)

Conv_Std_Logic_Vector(,)

580

(1)

Index

581

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Digital Logic and Microprocessor Design with VHDL

Summary

Table of Contents

Supplemental Materials