Handbook of 3D Integration, Volume 3 3D Process Technology

Edited by key figures in 3D integration and written by top authors from high-tech companies and renowned research institutions, this book covers the intricate details of 3D process technology. As such, the main focus is on silicon via formation, bonding and debonding, thinning, via reveal and backside processing, both from a technological and a materials science perspective. The last part of the book is concerned with assessing and enhancing the reliability of the 3D integrated devices, which is a prerequisite for the large-scale implementation of this emerging technology.
Invaluable reading for materials scientists, semiconductor physicists, and those working in the semiconductor industry, as well as IT and electrical engineers.

Philip Garrou is a consultant in the field of thin film microelectronic materials and applications, prior to which he was Director of Technology and New Business Development for Dow Chemicals' Advanced Electronic Materials business. He has authored two microelectronics texts and is co-author of over 75 peer reviewed publications and book chapters.

Mitsumasa Koyanagi is Professor in the Graduate School of Engineering at Tohoku University, Japan. After his PhD in electrical engineering he joined the Central Research Laboratory of Hitachi where he was engaged in the research on semiconductor memories. After a three-year stay at the Xerox Palo Alto Research Center in California, USA, he became Professor in the Research Center for Integrated Systems at Hiroshima University, Japan. Mitsumasa Koyanagi received numerous awards, including the Solid-State Devices and Materials Award.

Peter Ramm is head of the silicon technology department of the Fraunhofer Institute for Molecular Solid-State Technologies (EMFT) in Munich, Germany, where he is responsible for process integration of innovative devices and new materials. He received his Ph.D. in physics from the University of Regensburg and subsequently worked for Siemens before joining the Fraunhofer Institute for Solid State Technology (IFT) in Munich in 1988. He is the author or co-author of more than 50 papers and 20 patents.

Introduction -
Overview Since 2008
Drivers for 3D Integration
2.5D Interposer Technology
THROUGH SILICON VIA FORMATION
TSV Formation Overview
TSV Formation at Applied Materials
TSV Formation at ASET
TSV Fill by Wet Processing
TEMPORARY BONDING AND DEBONDING
Temporary Bonding: Materials and Requirements
Temporary Bonding and Debonding: Equipment and Processes
Temporary Bonding and Debonding at S?SS, EV Group, TOK
Electrostatic Chuck
THINNING, VIA REVEAL, BACKSIDE PROCESSING
Thinning
Via Reveal and Backside Processing
"Kiru, Kezuru and Migaku" (Dice, Grind and Polish)
Wafer Dicing -
Stealth Dicing
BONDING AND ASSEMBLY
Bonding and Assembly at Amkor, ASE, SCP, TSMC
Cu-Cu Direct Bonding
Oxide Bonding for BSI Imaging
Self Assembly
RELIABILITY ISSUES
3D Reliability Issues: Protrusion, Stress/Strain, Electromigration, Underfilling
Methodology of Reliability and Robustness for 3D Process Technology
Challenges in 3D Fabrication
Implications of Stress/Strain and Metal Contamination on Thinned Die
METROLOGY
Status of 2.5/3D Metrology