Advanced Metallization Conference 2007
, by McKerrow, Andrew J.; Shacham-Diamand, Yosi; Shingubara, Shoso; Shimogaki, Yukihiro
- ISBN: 9781558999923 | 1558999922
- Cover: Hardcover
- Copyright: 5/7/2008
The advanced metallization conference - held in albany, new york and tokyo, japan-marked its 24th annivarsary in 2007. These two sister coferences from a unique "one conference at two sites" that focuses on latest R&D and manufacturing results, as well as real-world integration and reliability data, on the application of metallization and related technologies for advanced IC devices.
| Possibilities and Problems of Self-Forming Barrier Process for Advanced LSI Metallization | p. 3 |
| A Surface Adsorption Limited Model of CoWBP Capping Barriers for sub 45 nm Cu Interconnects | p. 11 |
| Hybrid CoWP/SiCN Barriers Integration Using Hybrid Punch Through Approach | p. 17 |
| Copper and Copper Oxide Composite Films Deposited by ALD on Tantalum-Based Diffusion Barriers | p. 23 |
| Electroless Deposition of NiMoPB: Electrical Performances and Material Properties | p. 31 |
| PEALD WNC Thin Film as Electrode for MIM Capacitor | p. 39 |
| Diffusion Barriers Between Al and Cu for Cu Interconnects of Memory Devices | p. 45 |
| A Tomographic Approach for Precise Wafer Thinning for 3D Chip-Stacking, Photonic Interconnections, and Heat Removal Enhancement | p. 53 |
| Self-Restored Barrier Using Cu-Mn Alloy | p. 59 |
| Barrier Metal Integration for Copper Contacts on Nickel Silicide | p. 67 |
| Atomic Layer Deposition of Ru/TaNC Bi-Layer for Ultra-Thin CVD Cu Seed Formation | p. 75 |
| Dependence of Thermal Stability of NiSi/Si on Crystal Orientation | p. 81 |
| Highly (002) Preferred Ti Films Prepared by Hydrogen Introduced DC Magnetron Sputter Techniques | p. 89 |
| Quantitative Studies of Copper Diffusion Through Ultra-Thin ALD Tantalum Nitride Barrier Films by High Resolution-RBS | p. 95 |
| Contact Properties of Epitaxial NiSi[subscript 2]/Heavily Doped Si Structures Formed From Ni/Ti/Si Systems | p. 101 |
| Chemical Vapor Deposition of Ni-Pt Thin Film Using Pt(PF[subscript 3])[subscript 4] and Ni(PF[subscript 3])[subscript 4] | p. 107 |
| Investigation of ULK (k=2.5) Damage by Direct CMP Process for 45 nm Technology Node | p. 115 |
| Impact of Post Via Clean Solution on Self Aligned Barrier Integrity: Corrosion and Cu/Co Galvanic Coupling | p. 123 |
| Modeling Wafer Level Uniformity in Electrochemical-Mechanical Polishing (ECMP) | p. 131 |
| Analysis of Post-CMP Cleaning Mechanisms for Improving TDDB Reliability | p. 137 |
| Chemical Mechanical Polishing and Wet Cleaning Technologies of Ruthenium for Porous Low-k/Cu Interconnects | p. 143 |
| Electrochemical and Mechanical Characterization of Surface Reaction Layers for Copper and Various CMP Chemicals | p. 151 |
| Cu Planar Plating for CMP CoC Reduction | p. 157 |
| Drying Effect on Hydrophobic and Hydrophilic Films by IPA | p. 165 |
| Copper Contact Technology for sub-100 nm Contacts | p. 171 |
| Chemical Vapor Deposition of Amorphous Ruthenium-Phosphorus Alloy Films for Cu Interconnect Applications | p. 179 |
| Optical Measurement of Metal Film Thickness | p. 187 |
| Towards a Better Understanding of Organic Incorporation in Copper Electroplated Layers | p. 193 |
| Impurity Studies on Electroplated Copper Interconnects | p. 199 |
| Conformal Deposition and Gap-Filling of Copper Into Ultra Narrow Patterns by Supercritical Fluid Deposition | p. 207 |
| Topography-Sensitive Copper Deposition for "Post-Scalability" Regime - A Novel Nano-Selective Deposition Mode | p. 213 |
| Scaling of the Cu(Al) Seed Layer Thickness and Its Impact on the Specific Resistivity of sub-100 nm Interconnects | p. 221 |
| Three-Dimensional (3D) Characterization of Barrier/Seed Coverage in Via Using a Dedicated Scanning Transmission Electron Microscope (STEM) | p. 229 |
| Bottom-Up Via Filling by Metal Chloride Reduction Chemical Vapor Deposition (MCR-CVD) | p. 237 |
| A Study of the Electrical Resistivity Increase in Narrow and Thin Copper Interconnects | p. 245 |
| One Step Fabrication Method for Cu Thin Film on Insulator by Supercritical Fluid Deposition | p. 253 |
| The Kinetics of Cu[subscript 2]O-CVD Process for ULSI Interconnects | p. 259 |
| High Aspect-Ratio Pillar Structure with Gold Electroplating and STP Technique for Thick Multilevel Interconnections | p. 265 |
| Electrical Characteristics of Electrochemical Plated Cu Under Giga-Pascal Stresses | p. 271 |
| Structural Design of Cu Multi-Level Interconnects with Air-Gap by Finite Element Method | p. 279 |
| Circuit Performance Dependence on BEOL Processes and Variability | p. 285 |
| Restoration Solutions for Plasma-Damaged Ultra Low-k for the 45 nm Technology Node and Beyond | p. 293 |
| Evaluation of Airgap Structures Produced by Wet Etch of Sacrificial Dielectrics: Impact of Wet Etch Media on Diffusion Barriers, Copper, and the Cu/SiC:H Interface | p. 301 |
| High-Frequency Characteristics of On-Chip Wirings up to 110 GHz | p. 309 |
| Wafer-Level-Packaging Inductor with Extremely High Quality Factor and Its Application to 5.8 GHz LC-Type Voltage Controlled Oscillator | p. 315 |
| Signal Transmission Through Interconnects with Repetitive Loads | p. 321 |
| A Multilevel Copper/Low-k/Airgap BEOL Technology | p. 329 |
| Back-End Characterization: The Full Story | p. 337 |
| Challenges of Metals Integration for 45 nm and 32 nm From a Manufacturing Perspective | p. 347 |
| Integration of 50 nm Half Pitch Single Damascene Copper Trenches in Black Diamond II by Means of Double Patterning 193 nm Immersion Lithography on Metal Hardmask | p. 355 |
| 90 nm Generation RF CMOS Technology | p. 363 |
| Process Flow Development and Integration of Porous Low-k for 45 nm Node | p. 371 |
| BEOL Test Chip for Rapid Technology and Process Integration Debugging | p. 379 |
| CuAl Alloy: A Robust Solution for 45/32 nm Integration | p. 385 |
| Oxygen Distribution in Nickel Silicide Films Analyzed by Time-of-Flight Secondary Ion Mass Spectrometry | p. 391 |
| Directed Electroless Deposition (ELD) of Sub 50 nm Interconnects on Patterned Self-Assembled Monolayers (SAM) | p. 397 |
| Driving Metallization Dimensions to Sub-30 nm Using Immersion Lithography and a Self-Aligned Double Patterning Scheme | p. 403 |
| Air Gaps as a Viable Alternative for Low-k Dielectrics in Future Technology Nodes | p. 411 |
| Optimized Interfacial Strength for Dense and Porous SiCOH | p. 419 |
| Impact of Pore Density on Conduction Mechanisms in SiOCH Based Interconnects | p. 427 |
| UV, E-Beam, and Thermal Curing of Low-k Organosilicates: Effects on Glass Structure and Mechanical Properties | p. 433 |
| Development and Integration of a Porous ULK Dielectric (k=2.3 and below) for High Performance BEOL Interconnect | p. 439 |
| Dielectric Recoveries on O[subscript 2] Plasma Damaged Organosilicate Low-k Dielectrics | p. 447 |
| Depth Dependence of UV Curing of Organosilicate Low-k Thin Films | p. 455 |
| Highly Reliable Cu/ULK Integration Scheme Using MHM and Low-k Capping Film | p. 459 |
| Pore-Connectivity Dependence of Moisture Absorption Into Porous Low-k Films by Positron-Annihilation Lifetime Spectroscopy | p. 465 |
| The Integration of SOD as PMD for Sub-58 nm DRAM Technology Mode | p. 471 |
| Mechanical Properties of High-Temperature Vapor-Cured Ultra Low-k Film (Nanoclustering Silica k=2.0) | p. 477 |
| Effect of UV Cure on the Molecular Structure and Fracture Properties of an Ultra-Low-k Dielectric | p. 483 |
| Examining the Effects of UV Sources on Curing of Low-k Dielectrics Using Si[superscript 29] NMR | p. 489 |
| Directly Patterned Mesoporous Dielectric Films Templated From Chemically Amplified Block Copolymers | p. 495 |
| Parylene-X - A New Cross-Linkable 3D Wafer-to-Wafer Bonding Glue (and Flourinated Parylene-XF; A Stable ILD) | p. 501 |
| Structural Evolution of Nano-Porous Ultra-Low-k Dielectrics Under Broadband UV Curing | p. 507 |
| Process Induced Damages and Recovery by Silylation for Low-k/ Cu Interconnects with Highly-Porous Self-Assembled Silica Film | p. 513 |
| PBO/SiC Hybrid Structure with Ti Liner for Reliable Barrier-Free Interconnect | p. 521 |
| Mechanical Properties of High-Temperature Vapor-Cured Ultra Low-k Film (Nanoclustering Silica k=2.0) | p. 527 |
| Effect of UV Cure on Pore Interconnectivity of PECVD SiOC Films | p. 533 |
| Low Dielectric Constant Borazinic Films as Copper Diffusion Barrier Prepared by Pseudo-Remote Plasma Chemical Vapor Deposition | p. 539 |
| Robust Porous PE-CVD SiOC Film (k < 2.4) with Ultraviolet Curing for Cu/Low-k Multilevel Interconnect Fabrication | p. 545 |
| Evaluating Actual Plasma Damage in Ultra Low-k Materials for 45 nm nodes | p. 551 |
| TDDB Characteristics of Low-k Dielectrics After Plasma Damage Recovery Process | p. 557 |
| Integration of 140 nm Pitch Cu Interconnects Featuring Template-Type PE-CVD SiOC Film (k < 2.4) | p. 563 |
| Influence of Moisture Uptake in Porous PAr Film on Electrical Properties | p. 569 |
| Extraction of Metal Line Physicals and Its Application | p. 577 |
| New Expanded Equation Describing the Resistivity of Cu Interconnects with a Cu Alloy Seed Layer and Resistivity Calculation of 32 nm Node Cu Interconnects | p. 583 |
| Effect of Boron Behavior on the Adhesion Properties of Low Resistivity Tungsten Films | p. 589 |
| Modeling Electron Transport in Copper Interconnect Microstructures | p. 595 |
| Electrical Resistivity of Sub-100 nm Cu Films Deposited by Electroless on Self-Assembled Monolayer of Amino-Silane Activated with Au Nano-Particles | p. 601 |
| Evolution of Grain Size and Crystallographic Orientation in Narrow Lines | p. 607 |
| STP Technology - Interconnects, CMOS-MEMS, Packaging | p. 615 |
| Investigations on Via Geometry and Wetting Behavior for the Filling of Through Silicon Vias by Copper Electro Deposition | p. 623 |
| Table of Contents provided by Blackwell. All Rights Reserved. |
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